Datasheet ATM90E26 (Microchip) - 9

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Table-1 Pin Description (Continued) Name Pin No. I/O note 1 Type Description SDO: Serial Data Output of SPI
This pin is used as the data output for the SPI interface. Data on this pin is shifted out of the chip on the falling edge of SCLK. SDO/UTX 26 OZ LVTTL
UTX: UART Data Transmit
This pin is used to transmit data for the UART interface. This pin needs to be pulled up to VDD by a 10kΩ resistor.”
Note
: UART and SPI interface is selected by the USEL pin.
SDI: Serial Data Input of SPI
This pin is used as the data input for the SPI interface. Address and data on this pin is shifted into the chip on the rising edge of SCLK. SDI/URX 27 I LVTTL
URX: UART Data Receive
This pin is used to receive data for the UART interface.
Note
: UART and SPI interface is selected by the USEL pin.
MMD1/0: Metering Mode Configuration
00: anti-tampering mode (larger power); MMD1 1 I LVTTL 01: L line mode (fixed L line); MMD0 28 10: L+N mode (applicable for single-phase three-wire system); 11: flexible mode (line specified by the LNSel bit (MMode, 2BH))
OSCI: External Crystal Input
OSCI 22 I LVTTL An 8.192 MHz crystal is connected between OSCI and OSCO. In applica- tion, this pin should be connected to ground through a 12pF capacitor.
OSCO: External Crystal Output
OSCO 23 O LVTTL An 8.192 MHz crystal is connected between OSCI and OSCO. In applica- tion, this pin should be connected to ground through a 12pF capacitor.
CF1: Active Energy Pulse Output
CF1 18 O LVTTL
CF2: Reactive Energy Pulse Output
CF2 19 These pins output active/reactive energy pulses.
ZX: Voltage Zero-Crossing Output
This pin is asserted when voltage crosses zero. Zero-crossing mode can be ZX 21 O LVTTL configured to positive zero-crossing, negative zero-crossing or all zero- crossing by the Zxcon[1:0] bits (MMode, 2BH).
IRQ: Interrupt Output
This pin is asserted when one or more events in the SysStatus register IRQ 20 O LVTTL (01H) occur. It is deasserted when there is no bit set in the SysStatus regis- ter (01H).
WarnOut: Fatal Error Warning
WarnOut 17 O LVTTL This pin is asserted when there is metering parameter calibration error or voltage sag. Refer to section 4.3.
Reserved
Resv_Low 9 I LVTTL For normal operation, these pins should be connected to ground. 9 M90E26 [Datasheet] Atmel-46002B-SE-M90E26-Datasheet_110714 Document Outline Features Application Description Block Diagram 1 Pin Assignment 2 Pin Description 3 Functional Description 3.1 Dynamic Metering Range 3.2 Startup and No-Load Power 3.3 Energy Registers 3.4 N Line Metering and Anti-Tampering 3.4.1 Metering Mode and L/N Line Current Sampling Gain Configuration 3.4.2 Anti-Tampering Mode Threshold Compare Method Special Treatment at Low Power 3.5 Measurement and Zero-Crossing 3.5.1 Measurement 3.5.2 Zero-Crossing 3.6 Calibration 3.7 Reset 4 Interface 4.1 SPI Interface 4.1.1 Four-Wire Mode Read Sequence Write Sequence 4.1.2 Three-Wire Mode 4.1.3 Timeout and Protection 4.2 UART Interface 4.2.1 Byte Level Timing 4.2.2 Write Transaction 4.2.3 Read transaction 4.2.4 Checksum 4.3 WarnOut Pin for Fatal Error Warning 4.4 Low Cost Implementation in Isolation with MCU 5 Register 5.1 Register List 5.2 Status and Special Register SoftReset Software Reset SysStatus System Status FuncEn Function Enable SagTh Voltage Sag Threshold SmallPMod Small-Power Mode LastData Last Read/Write SPI/UART Value 5.3 Metering/ Measurement Calibration and Configuration 5.3.1 Metering Calibration and Configuration Register LSB RMS/Power 16-bit LSB CalStart Calibration Start Command PLconstH High Word of PL_Constant PLconstL Low Word of PL_Constant Lgain L Line Calibration Gain Lphi L Line Calibration Angle Ngain N Line Calibration Gain Nphi N Line Calibration Angle PStartTh Active Startup Power Threshold PNolTh Active No-Load Power Threshold QStartTh Reactive Startup Power Threshold QNolTh Reactive No-Load Power Threshold MMode Metering Mode Configuration CS1 Checksum 1 5.3.2 Measurement Calibration Register AdjStart Measurement Calibration Start Command Ugain Voltage rms Gain IgainL L Line Current rms Gain IgainN N Line Current rms Gain Uoffset Voltage Offset IoffsetL L Line Current Offset IoffsetN N Line Current Offset PoffsetL L Line Active Power Offset QoffsetL L Line Reactive Power Offset PoffsetN N Line Active Power Offset QoffsetN N Line Reactive Power Offset CS2 Checksum 2 5.4 Energy Register Theory of Energy Registers APenergy Forward Active Energy ANenergy Reverse Active Energy ATenergy Absolute Active Energy RPenergy Forward (Inductive) Reactive Energy RNenergy Reverse (Capacitive) Reactive Energy RTenergy Absolute Reactive Energy EnStatus Metering Status 5.5 Measurement Register Irms L Line Current rms Urms Voltage rms Pmean L Line Mean Active Power Qmean L Line Mean Reactive Power Freq Voltage Frequency PowerF L Line Power Factor Pangle Phase Angle between Voltage and L Line Current Smean L Line Mean Apparent Power Irms2 N Line Current rms Pmean2 N Line Mean Active Power Qmean2 N Line Mean Reactive Power PowerF2 N Line Power Factor Pangle2 Phase Angle between Voltage and N Line Current Smean2 N Line Mean Apparent Power 6 Electrical Specification 6.1 Electrical Specification 6.2 SPI Interface Timing 6.3 Power On Reset Timing 6.4 Zero-Crossing Timing 6.5 Voltage Sag Timing 6.6 Pulse Output 6.7 Absolute Maximum Rating Ordering Information Packaging Drawings Revision History