Datasheet TC1321 (Microchip) - 9

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TC1321 4.0 SERIAL PORT OPERATION 4.1 START Condition (START)
The Serial Clock input (SCL) and bi-directional data The TC1321 continuously monitors the SDA and SCL port (SDA) form a 2-wire bi-directional serial port for lines for a START condition (a HIGH to LOW transition programming and interrogating the TC1321. The of SDA while SCL is HIGH), and wil not respond until following conventions are used in this bus architecture. this condition is met.
TABLE 4-1: TC1321 SERIAL BUS 4.2 Address Byte CONVENTIONS
Immediately following the START condition, the host
Term Explanation
must transmit the address byte to the TC1321. The 7-bit SMBus address for the TC1321 is 1001000. The Transmitter The device sending data to the bus. 7-bit address transmitted in the serial bit stream must Receiver The device receiving data from the bus. match for the TC1321 to respond with an Acknowledge Master The device that controls the bus: initiating (indicating the TC1321 is on the bus and ready to transfers (START), generating the clock, and accept data). The eighth bit in the Address Byte is a terminating transfers (STOP) Read-Write bit. This bit is a 1 for a read operation or 0 Slave The device addressed by the master. for a write operation. During the first phase of any transfer, this bit will be set = 0 to indicate that the START A unique condition signaling the beginning of a transfer, indicated by SDA falling (High - command byte is being written. Low) while SCL is high. STOP A unique condition signaling the end of a
4.3 Acknowledge (ACK)
transfer, indicated by SDA rising (Low - High) Acknowledge (ACK) provides a positive handshake while SCL is high. between the host and the TC1321. The host releases ACK A receiver acknowledges the receipt of each SDA after transmitting eight bits, then generates a ninth byte with this unique condition. The receiver clock cycle to allow the TC1321 to pull the SDA line drives SDA low during SCL, high of the ACK LOW to Acknowledge that it successfully received the clock pulse.The master provides the clock previous eight bits of data or address. pulse for the ACK cycle. Busy Communication is not possible because the
4.4 Data Byte
bus is in use. Not Busy When the bus is IDLE, both SDA and SCL will After a successful ACK of the address byte, the host remain high. must transmit the data byte to be written or clock out Data Valid The state of SDA must remain stable during the data to be read. (See the appropriate timing the High period of SCL in order for a data bit diagrams.) ACK will be generated after a successful to be considered valid. SDA only changes write of a data byte into the TC1321. state while SCL is low during normal data transfers. See START and STOP conditions.
4.5 Stop Condition (STOP)
All transfers take place under control of a host, usually a CPU or microcontroller, acting as the master, which Communications must be terminated by a STOP provides the clock signal for all transfers. The TC1321 condition (a LOW to HIGH transition of SDA while SCL always operates as a slave. The serial protocol is is HIGH). The STOP condition must be communicated illustrated in Figure 4-1. All data transfers have two by the transmitter to the TC1321. Refer to Figure 4-1, phases; all bytes are transferred MSB first. Accesses for serial bus timing. are initiated by a START condition (START), followed by a device-address byte and one or more data bytes. The device-address byte includes a Read/Write selection bit. Each access must be terminated by a STOP Condition (STOP). A convention called Acknowledge (ACK) confirms receipt of each byte. Note that SDA can change only during periods when SCL is LOW (SDA changes while SCL is HIGH are reserved for START and STOP conditions).  2010 Microchip Technology Inc. DS21387C-page 9 Document Outline TC1321 10-Bit Digital-to-Analog Converter with Two-Wire Interface 1.0 Electrical Characteristics 2.0 Pin Descriptions TABLE 2-1: Pin Function Table 2.1 External Voltage Reference Input (VREF) 2.2 Bi-Directional Serial Data Input and Output (SDA) 2.3 Serial Clock Input (SCL) 2.4 Supply Power Ground (VSS) 2.5 Output (VOUT) 2.6 No Connection (NC) 2.7 Output (DAC-OUT) 2.8 Positive Power Supply Input (VDD) 3.0 Detailed Description 3.1 Reference Input 3.2 Output Amplifier 3.3 Standby Mode TABLE 3-1: Standby Mode Operation 3.4 SMBus Slave Address FIGURE 3-1: SMBus/I2C Protocols. 4.0 Serial Port Operation TABLE 4-1: TC1321 Serial Bus Conventions 4.1 START Condition (START) 4.2 Address Byte 4.3 Acknowledge (ACK) 4.4 Data Byte 4.5 Stop Condition (STOP) FIGURE 4-1: SMBus/I2CTiming Diagrams. 4.6 Register Set and Programmer’s Model TABLE 4-2: TC1321 Command Set (READ_BYTE and WRITE_BYTE) TABLE 4-3: Configuration Register (CONFIG), 8-Bit, Read/Write TABLE 4-4: Data Register (DATA), 10-Bit, Read/Write 4.7 Register Set Summary TABLE 4-5: TC1321 Register Set Summary 5.0 Packaging Information 5.1 Package Marking Information Appendix A: Revision History Product Identification System Worldwide Sales and Service