Datasheet TC1320 (Microchip) - 7

link to page 6 link to page 8
TC1320 4.0 SERIAL PORT OPERATION 4.1 START Condition (START)
The Serial Clock input (SCL) and bi-directional data The TC1320 continuously monitors the SDA and SCL port (SDA) form a 2-wire bi-directional serial port for lines for a START condition (a HIGH to LOW transition programming and interrogating the TC1320. The of SDA while SCL is HIGH), and will not respond until following conventions are used in this bus architecture: this condition is met.
TABLE 4-1: TC1320 SERIAL BUS 4.2 Address Byte CONVENTIONS
Immediately following the START Condition, the host must transmit the address byte to the TC1320. The
Term Explanation
7-bit SMBus address for the TC1320 is 1001000. The Transmitter The device sending data to the bus. 7-bit address transmitted in the serial bit stream must match for the TC1320 to respond with an Acknowledge Receiver The device receiving data from the bus. (indicating the TC1320 is on the bus and ready to Master The device which controls the bus: initiating accept data). The eighth bit in the Address Byte is a transfers (START), generating the clock, and Read/Write bit. This bit is a 1 for a read operation, or 0 terminating transfers (STOP). for a write operation. During the first phase of any Slave The device addressed by the master. transfer, this bit will be set = 0 to indicate that the START A unique condition signaling the beginning of command byte is being written. a transfer indicated by SDA falling (High - Low) while SCL is high.
4.3 Acknowledge (ACK)
STOP A unique condition signaling the end of a transfer indicated by SDA rising (Low - High) Acknowledge (ACK) provides a positive handshake while SCL is high. between the host and the TC1320. The host releases ACK A Receiver Acknowledges the receipt of each SDA after transmitting eight bits, then generates a ninth byte with this unique condition. The Receiver clock cycle to allow the TC1320 to pull the SDA line drives SDA low during SCL high of the ACK LOW to Acknowledge that it successfully received the clock pulse. The Master provides the clock previous eight bits of data or address. pulse for the ACK cycle. Busy Communication is not possible because the
4.4 Data Byte
bus is in use. After a successful ACK of the address byte, the host Not Busy When the bus is IDLE, both SDA and SCL will must transmit the data byte to be written, or clock out remain high. the data to be read. (See the appropriate timing dia- Data Valid The state of SDA must remain stable during grams.) ACK will be generated after a successful write the High period of SCL in order for a data bit of a data byte into the TC1320. to be considered valid. SDA only changes state while SCL is low during normal data transfers. (See START and STOP conditions.)
4.5 STOP Condition (STOP)
All transfers take place under control of a host, usually Communications must be terminated by a STOP con- a CPU or microcontroller, acting as the Master, which dition (a LOW to HIGH transition of SDA while SCL is provides the clock signal for all transfers. The TC1320 HIGH). The STOP Condition must be communicated always operates as a Slave. The serial protocol is illus- by the transmitter to the TC1320. Refer to Figure 4-1, trated in Figure 3-1. All data transfers have two phases; Timing Diagrams for serial bus timing. all bytes are transferred MSB first. Accesses are initi- ated by a START condition (START), followed by a device address byte and one or more data bytes. The device address byte includes a Read/Write selection bit. Each access must be terminated by a STOP Con- dition (STOP). A convention called Acknowledge (ACK) confirms receipt of each byte. Note that SDA can change only during periods when SCL is LOW (SDA changes while SCL is HIGH is reserved for START and STOP Conditions).  2002-2012 Microchip Technology Inc. DS21386C-page 7