Datasheet MCP4802, MCP4812, MCP4822 (Microchip) - 4

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MCP4802/4812/4822 ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Specifications:
Unless otherwise indicated, VDD = 5V, VSS = 0V, VREF = 2.048V, Output Buffer Gain (G) = 2x, RL = 5 k to GND, CL = 100 pF, TA = -40 to +85°C. Typical values are at +25°C.
Parameters Sym Min Typ Max Units Conditions Internal Voltage Reference (VREF)
Internal Reference Voltage VREF 2.008 2.048 2.088 V VOUTA when G = 1x and Code = 0xFFFh Temperature Coefficient VREF/°C — 125 325 ppm/°C -40°C to 0°C
(Note 2)
— 0.25 0.65 LSb/°C -40°C to 0°C — 45 160 ppm/°C 0°C to +85°C — 0.09 0.32 LSb/°C 0°C to +85°C Output Noise (VREF Noise) ENREF — 290 — µVp-p Code = 0xFFFh, G = 1x (0.1- 10 Hz) Output Noise Density eNREF — 1.2 — µV/Hz Code = 0xFFFh, G = 1x (1 kHz) eNREF — 1.0 — µV/Hz Code = 0xFFFh, G = 1x (10 kHz) 1/f Corner Frequency fCORNER — 400 — Hz
Output Amplifier
Output Swing VOUT — 0.01 to — V Accuracy is better than 1 LSb for VDD – 0.04 VOUT = 10 mV to (VDD–40 mV) Phase Margin PM — 66 — Degree CL= 400 pF, RL =  (°) Slew Rate SR — 0.55 — V/µs Short Circuit Current ISC — 15 24 mA Settling Time tSETTLING — 4.5 — µs Within 1/2 LSb of final value from 1/4 to 3/4 full-scale range
Dynamic Performance (Note 2)
DAC-to-DAC Crosstalk — <10 — nV-s Major Code Transition Glitch — 45 — nV-s 1 LSb change around major carry (0111...1111 to 1000...0000) Digital Feedthrough — <10 — nV-s Analog Crosstalk — <10 — nV-s
Note 1:
Guaranteed monotonic by design over all codes.
2:
This parameter is ensured by design, and not 100% tested. DS20002249B-page 4  2010-2015 Microchip Technology Inc. Document Outline 1.0 Electrical Characteristics FIGURE 1-1: SPI Input Timing Data. 2.0 Typical Performance Curves FIGURE 2-1: DNL vs. Code (MCP4822). FIGURE 2-2: DNL vs. Code and Temperature (MCP4822). FIGURE 2-3: Absolute DNL vs. Temperature (MCP4822). FIGURE 2-4: INL vs. Code and Temperature (MCP4822). FIGURE 2-5: Absolute INL vs. Temperature (MCP4822). FIGURE 2-6: INL vs. Code (MCP4822). FIGURE 2-7: DNL vs. Code and Temperature (MCP4812). FIGURE 2-8: INL vs. Code and Temperature (MCP4812). FIGURE 2-9: DNL vs. Code and Temperature (MCP4802). FIGURE 2-10: INL vs. Code and Temperature (MCP4802). FIGURE 2-11: Full-Scale VOUTA vs. Ambient Temperature and VDD. Gain = 1x. FIGURE 2-12: Full-Scale VOUTA vs. Ambient Temperature and VDD. Gain = 2x. FIGURE 2-13: Output Noise Voltage Density (VREF Noise Density) vs. Frequency. Gain = 1x. FIGURE 2-14: Output Noise Voltage (VREF Noise Voltage) vs. Bandwidth. Gain = 1x. FIGURE 2-15: IDD vs. Temperature and VDD. FIGURE 2-16: IDD Histogram (VDD = 2.7V). FIGURE 2-17: IDD Histogram (VDD = 5.0V). FIGURE 2-18: Software Shutdown Current vs. Temperature and VDD. FIGURE 2-19: Offset Error vs. Temperature and VDD. FIGURE 2-20: Gain Error vs. Temperature and VDD. FIGURE 2-21: VIN High Threshold vs. Temperature and VDD. FIGURE 2-22: VIN Low Threshold vs. Temperature and VDD. FIGURE 2-23: Input Hysteresis vs. Temperature and VDD. FIGURE 2-24: VOUT High Limit vs.Temperature and VDD. FIGURE 2-25: VOUT Low Limit vs. Temperature and VDD. FIGURE 2-26: IOUT High Short vs. Temperature and VDD. FIGURE 2-27: IOUT vs. VOUT. Gain = 2x. FIGURE 2-28: VOUT Rise Time. FIGURE 2-29: VOUT Fall Time. FIGURE 2-30: VOUT Rise Time. FIGURE 2-31: VOUT Rise Time. FIGURE 2-32: VOUT Rise Time Exit Shutdown. FIGURE 2-33: PSRR vs. Frequency. 3.0 Pin descriptions TABLE 3-1: Pin Function Table for MCP4802/4812/4822 3.1 Supply Voltage Pins (VDD, VSS) 3.2 Chip Select (CS) 3.3 Serial Clock Input (SCK) 3.4 Serial Data Input (SDI) 3.5 Latch DAC Input (LDAC) 3.6 Analog Outputs (VOUTA, VOUTB) 4.0 General Overview TABLE 4-1: LSb of each device FIGURE 4-1: Example for INL Error. FIGURE 4-2: Example for DNL Error. 4.1 Circuit Descriptions FIGURE 4-3: Typical Transient Response. FIGURE 4-4: Output Stage for Shutdown Mode. 5.0 Serial Interface 5.1 Overview 5.2 Write Command FIGURE 5-1: Write Command for MCP4822 (12-bit DAC). FIGURE 5-2: Write Command for MCP4812 (10-bit DAC). FIGURE 5-3: Write Command for MCP4802 (8-bit DAC). 6.0 Typical Applications 6.1 Digital Interface 6.2 Power Supply Considerations 6.3 Output Noise Considerations FIGURE 6-1: Typical Connection Diagram. 6.4 Layout Considerations 6.5 Single-Supply Operation 6.6 Bipolar Operation 6.7 Selectable Gain and Offset Bipolar Voltage Output Using a Dual Output DAC 6.8 Designing a Double-Precision DAC Using a Dual DAC 6.9 Building Programmable Current Source 7.0 Development support 7.1 Evaluation and Demonstration Boards 8.0 Packaging Information 8.1 Package Marking Information AMERICAS Corporate Office Atlanta Austin, TX Boston Chicago Cleveland Dallas Detroit Houston, TX Indianapolis Los Angeles New York, NY San Jose, CA Canada - Toronto ASIA/PACIFIC Asia Pacific Office Hong Kong Australia - Sydney China - Beijing China - Chengdu China - Chongqing China - Dongguan China - Hangzhou China - Hong Kong SAR China - Nanjing China - Qingdao China - Shanghai China - Shenyang China - Shenzhen China - Wuhan China - Xian ASIA/PACIFIC China - Xiamen China - Zhuhai India - Bangalore India - New Delhi India - Pune Japan - Osaka Japan - Tokyo Korea - Daegu Korea - Seoul Malaysia - Kuala Lumpur Malaysia - Penang Philippines - Manila Singapore Taiwan - Hsin Chu Taiwan - Kaohsiung Taiwan - Taipei Thailand - Bangkok EUROPE Austria - Wels Denmark - Copenhagen France - Paris Germany - Dusseldorf Germany - Munich Germany - Pforzheim Italy - Milan Italy - Venice Netherlands - Drunen Poland - Warsaw Spain - Madrid Sweden - Stockholm UK - Wokingham Worldwide Sales and Service