Datasheet MCP3202 (Microchip) - 9

MCP3202 Note:
Unless otherwise indicated, VDD = 5V, VSS = 0V, fSAMPLE = 100 ksps, fCLK = 18* fSAMPLE, TA = +25°C. 1.0 2.0 0.8 1.8
)
V
)
0.6 DD = 2.7V VDD = 5V
B
1.6 f
B S
SAMPLE = 50 ksps f 0.4
S
1.4 SAMPLE = 100 ksps
L (
0.2
r (L
1.2 0.0
ro
1.0
Error
-0.2 0.8
et Er
VDD = 2.7V -0.4
ain
0.6 f
G ffs
SAMPLE = 50 ksps -0.6
O
0.4 VDD = 5V -0.8 0.2 fSAMPLE = 100 -1.0 0.0 -50 -25 0 25 50 75 100 -50 -25 0 25 50 75 100
Temperature (°C) Temperature (°C) FIGURE 2-19:
Gain Error vs. Temperature.
FIGURE 2-22:
Offset Error vs. Temperature. 100 100 V 90 VDD = 5V 90 DD = 5V f 80 SAMPLE = 100 ksps 80 fSAMPLE = 100 ksps 70 70
B)
60
d
60 VDD = 2.7V 50 f 50 SAMPLE = 50 ksps
NR (dB)
V 40 40 DD = 2.7V
S INAD (
f 30
S
30 SAMPLE = 50 ksps 20 20 10 10 0 0 1 10 100 1 10 100
Input Frequency (kHz) Input Frequency (kHz) FIGURE 2-20:
Signal-to-Noise Ratio
FIGURE 2-23:
Signal-to-Noise and (SNR) vs. Input Frequency. Distortion (SINAD) vs. Input Frequency. 0 80 -10 VDD = 5V 70 f -20 SAMPLE = 100 ksps 60 -30
B) B)
-40
d
V 50 DD = 2.7V
d
VDD = 2.7V -50
D (
fSAMPLE = 50 ksps
D (
40 fSAMPLE = 50 ksps -60
TH
30
INA
-70
S
-80 20 VDD = 5V -90 f 10 SAMPLE = 100 ksps -100 0 1 10 100 -40 -35 -30 -25 -20 -15 -10 -5 0
Input Frequency (kHz) Input Signal Level (dB) FIGURE 2-21:
Total Harmonic Distortion
FIGURE 2-24:
Signal-to-Noise and (THD) vs. Input Frequency. Distortion (SINAD) vs. Signal Level.  1999-2011 Microchip Technology Inc. DS21034F-page 9 Document Outline MCP3202 - 2.7V Dual Channel 12-Bit A/D Converter with SPI Serial Interface Functional Block Diagram Package Types 1.0 Electrical Characteristics Absolute Maximum Ratings † FIGURE 1-1: Serial Timing. FIGURE 1-2: Test Circuits. 2.0 Typical Performance Characteristics FIGURE 2-1: Integral Nonlinearity (INL) vs. Sample Rate. FIGURE 2-2: Integral Nonlinearity (INL) vs. VDD. FIGURE 2-3: Integral Nonlinearity (INL) vs. Code (Representative Part). FIGURE 2-4: Integral Nonlinearity (INL) vs. Sample Rate (VDD = 2.7V). FIGURE 2-5: Integral Nonlinearity (INL) vs. VDD. FIGURE 2-6: Integral Nonlinearity (INL) vs. Code (Representative Part, VDD = 2.7V). FIGURE 2-7: Integral Nonlinearity (INL) vs. Temperature. FIGURE 2-8: Differential Nonlinearity (DNL) vs. Sample Rate. FIGURE 2-9: Differential Nonlinearity (DNL) vs. VDD. FIGURE 2-10: Integral Nonlinearity (INL) vs. Temperature (VDD = 2.7V). FIGURE 2-11: Differential Nonlinearity (DNL) vs. Sample Rate (VDD = 2.7V). FIGURE 2-12: Differential Nonlinearity (DNL) vs. VDD. FIGURE 2-13: Differential Nonlinearity (DNL) vs. Code (Representative Part). FIGURE 2-14: Differential Nonlinearity (DNL) vs. Temperature. FIGURE 2-15: Gain Error vs. VDD. FIGURE 2-16: Differential Nonlinearity (DNL) vs. Code (Representative Part, VDD = 2.7V). FIGURE 2-17: Differential Nonlinearity (DNL) vs. Temperature (VDD = 2.7V). FIGURE 2-18: Offset Error vs. VDD. FIGURE 2-19: Gain Error vs. Temperature. FIGURE 2-20: Signal-to-Noise Ratio (SNR) vs. Input Frequency. FIGURE 2-21: Total Harmonic Distortion (THD) vs. Input Frequency. FIGURE 2-22: Offset Error vs. Temperature. FIGURE 2-23: Signal-to-Noise and Distortion (SINAD) vs. Input Frequency. FIGURE 2-24: Signal-to-Noise and Distortion (SINAD) vs. Signal Level. FIGURE 2-25: Effective Number of Bits (ENOB) vs. VDD. FIGURE 2-26: Spurious Free Dynamic Range (SFDR) vs. Input Frequency. FIGURE 2-27: Frequency Spectrum of 10 kHz input (Representative Part). FIGURE 2-28: Effective Number of Bits (ENOB) vs. Input Frequency. FIGURE 2-29: Power Supply Rejection (PSR) vs. Ripple Frequency. FIGURE 2-30: Frequency Spectrum of 1 kHz input (Representative Part, VDD = 2.7V). FIGURE 2-31: IDD vs. VDD. FIGURE 2-32: IDD vs. Clock Frequency. FIGURE 2-33: IDD vs. Temperature. FIGURE 2-34: IDDS vs. VDD. FIGURE 2-35: IDDS vs. Temperature. FIGURE 2-36: Analog Input leakage current vs. Temperature. 3.0 Pin Descriptions TABLE 3-1: Pin Function Table 3.1 Analog Inputs (CH0/CH1) 3.2 Chip Select/Shutdown (CS/SHDN) 3.3 Serial Clock (CLK) 3.4 Serial Data Input (DIN) 3.5 Serial Data Output (DOUT) 4.0 Device Operation 4.1 Analog Inputs 4.2 Digital Output Code EQUATION 4-1: FIGURE 4-1: Analog Input Model. FIGURE 4-2: Maximum Clock Frequency vs. Input Resistance (RS) to maintain less than a 0.1 LSB deviation in INL from nominal conditions. 5.0 Serial Communications 5.1 Overview TABLE 5-1: Configuration Bits for the MCP3202 FIGURE 5-1: Communication with the MCP3202 using MSB first format only. FIGURE 5-2: Communication with MCP3202 using LSB first format. 6.0 Applications Information 6.1 Using the MCP3202 with Microcontroller (MCU) SPI Ports FIGURE 6-1: SPI Communication using 8-bit segments (Mode 0,0: SCLK idles low). FIGURE 6-2: SPI Communication using 8-bit segments (Mode 1,1: SCLK idles high). 6.2 Maintaining Minimum Clock Speed 6.3 Buffering/Filtering the Analog Inputs FIGURE 6-3: The MCP601 Operational Amplifier is used to implement a 2nd order anti- aliasing filter for the signal being converted by the MCP3202. 6.4 Layout Considerations FIGURE 6-4: VDD traces arranged in a ‘Star’ configuration in order to reduce errors caused by current return paths. 7.0 Packaging Information 7.1 Package Marking Information Appendix A: Revision History Worldwide Sales and Service