Technical Reference Manual ARM926EJ-S (r0p4/r0p5) (Microchip) - 8

link to page 58 link to page 58 link to page 60 link to page 62 link to page 63 link to page 68 link to page 73 link to page 74 link to page 75 link to page 76 link to page 77 link to page 79 link to page 80 link to page 86 link to page 87 link to page 88 link to page 88 link to page 101 link to page 101 link to page 102 link to page 102 link to page 104 link to page 104 link to page 106 link to page 114 link to page 144 link to page 145 link to page 161 link to page 167 link to page 182 link to page 184 link to page 191 link to page 193 link to page 195 link to page 197 link to page 198 link to page 200 link to page 202 link to page 209 link to page 211 link to page 211 link to page 212 link to page 213 link to page 214 link to page 215 link to page 217 link to page 218 List of Tables Table 2-23 TCM Region Register c9 .. 2-30 Table 2-24 TCM Size field encoding ... 2-30 Table 2-25 Programming the TLB Lockdown Register ... 2-32 Table 2-26 FCSE PID Register operations ... 2-34 Table 2-27 Context ID register operations .. 2-35 Table 3-1 MMU program-accessible CP15 registers .. 3-4 Table 3-2 First-level descriptor bits ... 3-9 Table 3-3 Interpreting first-level descriptor bits [1:0] ... 3-10 Table 3-4 Section descriptor bits .. 3-11 Table 3-5 Coarse page table descriptor bits ... 3-12 Table 3-6 Fine page table descriptor bits .. 3-13 Table 3-7 Second-level descriptor bits .. 3-15 Table 3-8 Interpreting page table entry bits [1:0] .. 3-16 Table 3-9 Priority encoding of fault status ... 3-22 Table 3-10 FAR values for multi-word transfers ... 3-23 Table 3-11 Domain access control register, access control bits ... 3-24 Table 3-12 Interpreting access permission (AP) bits .. 3-24 Table 4-1 CP15 c1 I and M bit settings for the ICache ... 4-5 Table 4-2 Page table C bit settings for the ICache ... 4-5 Table 4-3 CP15 c1 C and M bit settings for the DCache .. 4-6 Table 4-4 Page table C and B bit settings for the DCache ... 4-6 Table 4-5 Instruction access priorities to the TCM and cache .. 4-8 Table 4-6 Data access priorities to the TCM and cache ... 4-8 Table 4-7 Values of S and NSETS ... 4-10 Table 5-1 Relationship between DMDMAEN, DRDMACS, and DRIDLE ... 5-6 Table 6-1 Supported HBURST encodings .. 6-4 Table 6-2 IHPROT[3:0] and DHPROT[3:0] attributes ... 6-5 Table 8-1 Handshake signal encoding .. 8-5 Table 8-2 CPBURST encoding ... 8-11 Table 11-1 Scan chain 15 format .. 11-2 Table 11-2 Scan chain 15 mapping to CP15 registers ... 11-4 Table A-1 AHB related signals .. A-3 Table A-2 Coprocessor interface signals .. A-5 Table A-3 Debug signals ... A-7 Table A-4 JTAG signals .. A-9 Table A-5 Miscellaneous signals ... A-10 Table A-6 ETM interface signals ... A-12 Table A-7 TCM interface signals ... A-14 Table B-1 Debug Override Register .. B-3 Table B-2 Trace Control Register bit assignments .. B-5 Table B-3 MMU test operation instructions ... B-5 Table B-4 Encoding of the main TLB entry-select bit fields ... B-6 Table B-5 Encoding of the TLB MVA tag bit fields .. B-7 Table B-6 Encoding of the TLB entry PA and AP bit fields ... B-8 Table B-7 Main TLB mapping to MMUxWD .. B-9 Table B-8 Encoding of the lockdown TLB entry-select bit fields ... B-11 Table B-9 Cache Debug Control Register bit assignments ... B-12 viii Copyright © 2001-2003 ARM Limited. All rights reserved. ARM DDI0198D Document Outline Contents List of Tables List of Figures Preface About this manual Product revision status Intended audience Using this manual Conventions Further reading Feedback Feedback on the product Feedback on this manual Introduction 1.1 About the ARM926EJ-S processor Programmer’s Model 2.1 About the programmer’s model 2.2 Summary of ARM926EJ-S system control coprocessor (CP15) registers 2.2.1 Addresses in an ARM926EJ-S system 2.2.2 Accessing CP15 registers 2.3 Register descriptions 2.3.1 ID Code, Cache Type, and TCM Status Registers, c0 2.3.2 Control Register c1 2.3.3 Translation Table Base Register c2 2.3.4 Domain Access Control Register c3 2.3.5 Register c4 2.3.6 Fault Status Registers c5 2.3.7 Fault Address Register c6 2.3.8 Cache Operations Register c7 2.3.9 TLB Operations Register c8 2.3.10 Cache Lockdown and TCM Region Registers c9 2.3.11 TLB Lockdown Register c10 2.3.12 Register c11 and c12 2.3.13 Process ID Register c13 2.3.14 Register c14 2.3.15 Test and Debug Register c15 Memory Management Unit 3.1 About the MMU 3.1.1 Access permissions and domains 3.1.2 Translated entries 3.1.3 MMU program accessible registers 3.2 Address translation 3.2.1 Translation table base 3.2.2 First-level fetch 3.2.3 First-level descriptor 3.2.4 Section descriptor 3.2.5 Coarse page table descriptor 3.2.6 Fine page table descriptor 3.2.7 Translating section references 3.2.8 Second-level descriptor 3.2.9 Translating large page references 3.2.10 Translating small page references 3.2.11 Translating tiny page references 3.3 MMU faults and CPU aborts 3.3.1 Fault address and fault status registers 3.4 Domain access control 3.5 Fault checking sequence 3.5.1 Alignment faults 3.5.2 Translation faults 3.5.3 Domain faults 3.5.4 Permission faults 3.6 External aborts 3.6.1 Enabling the MMU 3.6.2 Disabling the MMU 3.7 TLB structure Caches and Write Buffer 4.1 About the caches and write buffer 4.2 Write buffer 4.3 Enabling the caches 4.4 TCM and cache access priorities 4.5 Cache MVA and Set/Way formats Tightly-Coupled Memory Interface 5.1 About the tightly-coupled memory interface 5.2 TCM interface signals 5.2.1 Data interface signals 5.2.2 Instruction TCM signals 5.2.3 Differences between DTCM and ITCM 5.3 TCM interface bus cycle types and timing 5.3.1 Zero wait state timing 5.3.2 DMA access to zero wait state TCM 5.3.3 Multi-cycle access timing 5.4 TCM programmer’s model 5.4.1 Enabling the ITCM 5.4.2 Enabling the DTCM 5.4.3 Disabling the ITCM 5.4.4 Disabling the DTCM 5.4.5 Cachable and bufferable attributes 5.5 TCM interface examples 5.5.1 Zero-wait-state RAM example 5.5.2 Producing byte writable memory using word writable RAM 5.5.3 Multiple banks of RAM example 5.5.4 Sequential ROM example 5.5.5 DMA interface example 5.5.6 Integrating RAM test logic 5.6 TCM access penalties 5.7 TCM write buffer 5.8 Using synchronous SRAM as TCM memory 5.9 TCM clock gating Bus Interface Unit 6.1 About the bus interface unit 6.2 Supported AHB transfers 6.2.1 Memory map 6.2.2 Transfer size 6.2.3 Mapping of level one and level two (AHB) attributes 6.2.4 Byte and halfword accesses 6.2.5 AHB system considerations 6.2.6 AHB clocking 6.2.7 External Abort limitations Noncachable Instruction Fetches 7.1 About noncachable instruction fetches 7.1.1 Uses of noncachable code 7.1.2 Self modifying code 7.1.3 AHB behavior Coprocessor Interface 8.1 About the ARM926EJ-S external coprocessor interface 8.1.1 Overview 8.2 LDC/STC 8.3 MCR/MRC 8.3.1 Interlocked MCR 8.4 CDP 8.5 Privileged instructions 8.6 Busy-waiting and interrupts 8.7 CPBURST 8.8 CPABORT 8.9 nCPINSTRVALID 8.10 Connecting multiple external coprocessors Instruction Memory Barrier 9.1 About the instruction memory barrier operation 9.2 IMB operation 9.2.1 Clean the DCache 9.2.2 Drain the write buffer 9.2.3 Synchronize data and instruction streams in level two AHB subsystems 9.2.4 Invalidate the ICache 9.2.5 Flush the prefetch buffer 9.3 Example IMB sequences Embedded Trace Macrocell Support 10.1 About Embedded Trace Macrocell support 10.1.1 FIFOFULL Debug Support 11.1 About debug support 11.1.1 Debug clocks 11.1.2 Scan chain 15 Power Management 12.1 About power management 12.1.1 Dynamic power management (wait for interrupt mode) 12.1.2 Static power management (leakage control) Signal Descriptions A.1 Signal properties and requirements A.2 AHB related signals A.3 Coprocessor interface signals A.4 Debug signals A.5 JTAG signals A.6 Miscellaneous signals A.7 ETM interface signals A.8 TCM interface signals CP15 Test and Debug Registers B.1 About the Test and Debug Registers B.1.1 Debug Override Register B.1.2 Debug and Test Address Register B.1.3 Trace Control Register B.1.4 MMU test operations B.1.5 Cache Debug Control Register B.1.6 MMU Debug Control Register B.1.7 Memory Region Remap Register Glossary Index A B C D E F H I J L M N O P R S T U V W Z