Technical Reference Manual ARM926EJ-S (r0p4/r0p5) (Microchip) - 3

link to page 15 link to page 16 link to page 21 link to page 23 link to page 24 link to page 29 link to page 30 link to page 31 link to page 35 link to page 65 link to page 66 link to page 69 link to page 85 link to page 88 link to page 90 link to page 93 link to page 95 Contents
ARM926EJ-S Technical Reference Manual Preface
About this manual .. xvi Feedback ... xxi
Chapter 1 Introduction
1.1 About the ARM926EJ-S processor ... 1-2
Chapter 2 Programmer’s Model
2.1 About the programmer’s model ... 2-2 2.2 Summary of ARM926EJ-S system control coprocessor (CP15) registers .. 2-3 2.3 Register descriptions .. 2-7
Chapter 3 Memory Management Unit
3.1 About the MMU ... 3-2 3.2 Address translation ... 3-5 3.3 MMU faults and CPU aborts ... 3-21 3.4 Domain access control .. 3-24 3.5 Fault checking sequence .. 3-26 3.6 External aborts .. 3-29 3.7 TLB structure .. 3-31 ARM DDI0198D Copyright © 2001-2003 ARM Limited. All rights reserved. iii Document Outline Contents List of Tables List of Figures Preface About this manual Product revision status Intended audience Using this manual Conventions Further reading Feedback Feedback on the product Feedback on this manual Introduction 1.1 About the ARM926EJ-S processor Programmer’s Model 2.1 About the programmer’s model 2.2 Summary of ARM926EJ-S system control coprocessor (CP15) registers 2.2.1 Addresses in an ARM926EJ-S system 2.2.2 Accessing CP15 registers 2.3 Register descriptions 2.3.1 ID Code, Cache Type, and TCM Status Registers, c0 2.3.2 Control Register c1 2.3.3 Translation Table Base Register c2 2.3.4 Domain Access Control Register c3 2.3.5 Register c4 2.3.6 Fault Status Registers c5 2.3.7 Fault Address Register c6 2.3.8 Cache Operations Register c7 2.3.9 TLB Operations Register c8 2.3.10 Cache Lockdown and TCM Region Registers c9 2.3.11 TLB Lockdown Register c10 2.3.12 Register c11 and c12 2.3.13 Process ID Register c13 2.3.14 Register c14 2.3.15 Test and Debug Register c15 Memory Management Unit 3.1 About the MMU 3.1.1 Access permissions and domains 3.1.2 Translated entries 3.1.3 MMU program accessible registers 3.2 Address translation 3.2.1 Translation table base 3.2.2 First-level fetch 3.2.3 First-level descriptor 3.2.4 Section descriptor 3.2.5 Coarse page table descriptor 3.2.6 Fine page table descriptor 3.2.7 Translating section references 3.2.8 Second-level descriptor 3.2.9 Translating large page references 3.2.10 Translating small page references 3.2.11 Translating tiny page references 3.3 MMU faults and CPU aborts 3.3.1 Fault address and fault status registers 3.4 Domain access control 3.5 Fault checking sequence 3.5.1 Alignment faults 3.5.2 Translation faults 3.5.3 Domain faults 3.5.4 Permission faults 3.6 External aborts 3.6.1 Enabling the MMU 3.6.2 Disabling the MMU 3.7 TLB structure Caches and Write Buffer 4.1 About the caches and write buffer 4.2 Write buffer 4.3 Enabling the caches 4.4 TCM and cache access priorities 4.5 Cache MVA and Set/Way formats Tightly-Coupled Memory Interface 5.1 About the tightly-coupled memory interface 5.2 TCM interface signals 5.2.1 Data interface signals 5.2.2 Instruction TCM signals 5.2.3 Differences between DTCM and ITCM 5.3 TCM interface bus cycle types and timing 5.3.1 Zero wait state timing 5.3.2 DMA access to zero wait state TCM 5.3.3 Multi-cycle access timing 5.4 TCM programmer’s model 5.4.1 Enabling the ITCM 5.4.2 Enabling the DTCM 5.4.3 Disabling the ITCM 5.4.4 Disabling the DTCM 5.4.5 Cachable and bufferable attributes 5.5 TCM interface examples 5.5.1 Zero-wait-state RAM example 5.5.2 Producing byte writable memory using word writable RAM 5.5.3 Multiple banks of RAM example 5.5.4 Sequential ROM example 5.5.5 DMA interface example 5.5.6 Integrating RAM test logic 5.6 TCM access penalties 5.7 TCM write buffer 5.8 Using synchronous SRAM as TCM memory 5.9 TCM clock gating Bus Interface Unit 6.1 About the bus interface unit 6.2 Supported AHB transfers 6.2.1 Memory map 6.2.2 Transfer size 6.2.3 Mapping of level one and level two (AHB) attributes 6.2.4 Byte and halfword accesses 6.2.5 AHB system considerations 6.2.6 AHB clocking 6.2.7 External Abort limitations Noncachable Instruction Fetches 7.1 About noncachable instruction fetches 7.1.1 Uses of noncachable code 7.1.2 Self modifying code 7.1.3 AHB behavior Coprocessor Interface 8.1 About the ARM926EJ-S external coprocessor interface 8.1.1 Overview 8.2 LDC/STC 8.3 MCR/MRC 8.3.1 Interlocked MCR 8.4 CDP 8.5 Privileged instructions 8.6 Busy-waiting and interrupts 8.7 CPBURST 8.8 CPABORT 8.9 nCPINSTRVALID 8.10 Connecting multiple external coprocessors Instruction Memory Barrier 9.1 About the instruction memory barrier operation 9.2 IMB operation 9.2.1 Clean the DCache 9.2.2 Drain the write buffer 9.2.3 Synchronize data and instruction streams in level two AHB subsystems 9.2.4 Invalidate the ICache 9.2.5 Flush the prefetch buffer 9.3 Example IMB sequences Embedded Trace Macrocell Support 10.1 About Embedded Trace Macrocell support 10.1.1 FIFOFULL Debug Support 11.1 About debug support 11.1.1 Debug clocks 11.1.2 Scan chain 15 Power Management 12.1 About power management 12.1.1 Dynamic power management (wait for interrupt mode) 12.1.2 Static power management (leakage control) Signal Descriptions A.1 Signal properties and requirements A.2 AHB related signals A.3 Coprocessor interface signals A.4 Debug signals A.5 JTAG signals A.6 Miscellaneous signals A.7 ETM interface signals A.8 TCM interface signals CP15 Test and Debug Registers B.1 About the Test and Debug Registers B.1.1 Debug Override Register B.1.2 Debug and Test Address Register B.1.3 Trace Control Register B.1.4 MMU test operations B.1.5 Cache Debug Control Register B.1.6 MMU Debug Control Register B.1.7 Memory Region Remap Register Glossary Index A B C D E F H I J L M N O P R S T U V W Z