Datasheet PIC12(L)F1612/16(L)F1613 (Microchip) - 2

PIC12(L)F1612/16(L)F1613
• Up to 11 I/O Pins and One Input-only Pin:
Clocking Structure
- Individually programmable pull-ups - Slew rate control • 16 MHz Internal Oscillator: - Interrupt-on-change with edge-select - ±1% at calibration - Selectable frequency range from 32 MHz to 31 kHz
Intelligent Analog Peripherals
• 31 kHz Low-Power Internal Oscillator • 10-Bit Analog-to-Digital Converter (ADC): • 4x Phase-Locked Loop (PLL): - Up to 8 external channels - For up to 32 MHz internal operation - Conversion available during Sleep • External Oscillator Block with: • Up to Two Comparators (COMP): - Three external clock modes up to 32 MHz - Low-Power/High-Speed mode - Up to three external inverting inputs - Fixed Voltage Reference at non-inverting input(s) - Comparator outputs externally accessible • 8-Bit Digital-to-Analog Converter (DAC): - 8-bit resolution, rail-to-rail - Positive Reference Selection • Voltage Reference: - Fixed Voltage Reference (FVR): 1.024V, 2.048V and 4.096V output levels • Zero-Cross Detect (ZCD): - Detect when AC signal on pin crosses ground • Two High-Current Drive Pins: - 100mA @ 5V  2014-2017 Microchip Technology Inc. DS40001737C-page 2 Document Outline Description TABLE 1: PIC12/16(L)F161x Family Types TABLE 2: Packages TABLE 3: 8-Pin Allocation Table (PIC12(L)F1612) TABLE 4: 14/16-Pin Allocation Table (PIC16(L)F1613) Table of Contents 8/14-Pin, 8-Bit Flash Microcontroller 1.0 Device Overview TABLE 1-1: Device Peripheral Summary 1.1 Register and Bit Naming Conventions FIGURE 1-1: PIC12(L)F1612/16(L)F1613 Block Diagram TABLE 1-2: PIC12(L)F1612 Pinout Description TABLE 1-3: PIC16(L)F1613 Pinout Description 2.0 Enhanced Mid-Range CPU FIGURE 2-1: Core Block Diagram 2.1 Automatic Interrupt Context Saving 2.2 16-Level Stack with Overflow and Underflow 2.3 File Select Registers 2.4 Instruction Set 3.0 Memory Organization 3.1 Program Memory Organization 3.2 High-Endurance Flash FIGURE 3-1: Program Memory Map and Stack for PIC12(L)F1612/16(L)F1613 EXAMPLE 3-1: RETLW Instruction EXAMPLE 3-2: Accessing Program Memory Via FSR 3.3 Data Memory Organization TABLE 3-1: Core Registers Register 3-1: STATUS: STATUS Register FIGURE 3-2: Banked Memory Partitioning TABLE 3-2: PIC12(L)F1612 Memory Map, Bank 0-7 TABLE 3-3: PIC16(L)F1613 Memory Map, Bank 0-7 TABLE 3-4: PIC12(L)F1612/16(L)F1613 Memory Map, Bank 8-23 TABLE 3-5: PIC12(L)F1612/16(L)F1613 Memory Map, Bank 24-31 TABLE 3-6: PIC12(L)F1612/16(L)F1613 Memory Map, Bank 27 TABLE 3-7: PIC12(L)F1612/16(L)F1613 Memory Map, Bank 31 TABLE 3-8: Core Function Registers Summary TABLE 3-9: Special Function Register Summary 3.4 PCL and PCLATH FIGURE 3-3: Loading of PC in Different Situations 3.5 Stack FIGURE 3-4: Accessing the Stack Example 1 FIGURE 3-5: Accessing the Stack Example 2 FIGURE 3-6: Accessing the Stack Example 3 FIGURE 3-7: Accessing the Stack Example 4 3.6 Indirect Addressing FIGURE 3-8: Indirect Addressing FIGURE 3-9: Traditional Data Memory Map FIGURE 3-10: Linear Data Memory Map FIGURE 3-11: Program Flash Memory Map 4.0 Device Configuration 4.1 Configuration Words 4.2 Register Definitions: Configuration Words Register 4-1: CONFIG1: Configuration Word 1 Register 4-2: CONFIG2: Configuration Word 2 Register 4-3: CONFIG3: Configuration Word 3 4.3 Code Protection 4.4 Write Protection 4.5 User ID 4.6 Device ID and Revision ID 4.7 Register Definitions: Device ID Register 4-4: DevID: Device ID Register Register 4-5: RevID: Revision ID Register 5.0 Oscillator Module 5.1 Overview FIGURE 5-1: Simplified PIC® MCU Clock Source Block Diagram 5.2 Clock Source Types FIGURE 5-2: External Clock (EC) Mode Operation FIGURE 5-3: Internal Oscillator Switch Timing 5.3 Clock Switching TABLE 5-1: Oscillator Switching Delays 5.4 Register Definitions: Oscillator Control Register 5-1: OSCCON: Oscillator Control Register Register 5-2: OSCSTAT: Oscillator Status Register Register 5-3: OSCTUNE: Oscillator Tuning Register TABLE 5-2: Summary of Registers Associated with Clock Sources TABLE 5-3: Summary of Configuration Word with Clock Sources 6.0 Resets FIGURE 6-1: Simplified Block Diagram of On-Chip Reset Circuit 6.1 Power-On Reset (POR) 6.2 Brown-Out Reset (BOR) TABLE 6-1: BOR Operating Modes FIGURE 6-2: Brown-out Situations 6.3 Register Definitions: BOR Control Register 6-1: BORCON: Brown-out Reset Control Register 6.4 Low-Power Brown-Out Reset (LPBOR) 6.5 MCLR TABLE 6-2: MCLR Configuration 6.6 Watchdog Timer (WDT) Reset 6.7 RESET Instruction 6.8 Stack Overflow/Underflow Reset 6.9 Programming Mode Exit 6.10 Power-Up Timer 6.11 Start-up Sequence FIGURE 6-3: Reset Start-up Sequence 6.12 Determining the Cause of a Reset TABLE 6-3: Reset Status Bits and Their Significance TABLE 6-4: Reset Condition for Special Registers 6.13 Power Control (PCON) Register 6.14 Register Definitions: Power Control Register 6-2: PCON: Power Control Register TABLE 6-5: Summary of Registers Associated with Resets TABLE 6-6: Summary of Configuration Word with Resets 7.0 Interrupts FIGURE 7-1: Interrupt Logic 7.1 Operation 7.2 Interrupt Latency FIGURE 7-2: Interrupt Latency FIGURE 7-3: INT Pin Interrupt Timing 7.3 Interrupts During Sleep 7.4 INT Pin 7.5 Automatic Context Saving 7.6 Register Definitions: Interrupt Control Register 7-1: INTCON: Interrupt Control Register Register 7-2: PIE1: Peripheral Interrupt Enable Register 1 Register 7-3: PIE2: Peripheral Interrupt Enable Register 2 Register 7-4: PIE3: Peripheral Interrupt Enable Register 3 Register 7-5: PIE4: Peripheral Interrupt Enable Register 4 Register 7-6: PIR1: Peripheral Interrupt Request Register 1 Register 7-7: PIR2: Peripheral Interrupt Request Register 2 Register 7-8: PIR3: Peripheral Interrupt Request Register 3 Register 7-9: PIR4: Peripheral Interrupt Request Register 4 TABLE 7-1: Summary of Registers Associated with Interrupts 8.0 Power-Down Mode (Sleep) 8.1 Wake-up from Sleep FIGURE 8-1: Wake-up from Sleep through Interrupt 8.2 Low-Power Sleep Mode 8.3 Register Definitions: Voltage Regulator Control Register 8-1: VREGCON: Voltage Regulator Control Register(1) TABLE 8-1: Summary of Registers Associated with Power-Down Mode 9.0 Windowed Watchdog Timer (WDT) FIGURE 9-1: Watchdog Timer Block Diagram 9.1 Independent Clock Source 9.2 WDT Operating Modes TABLE 9-1: WDT Operating Modes 9.3 Time-Out Period 9.4 Watchdog Window 9.5 Clearing the WDT 9.6 Operation During Sleep TABLE 9-2: WDT Clearing Conditions FIGURE 9-2: Window Period and Delay 9.7 Register Definitions: Windowed Watchdog Timer Control Register 9-1: WDTCON0: Watchdog Timer Control Register 0 Register 9-2: WDTCON1: Watchdog Timer Control Register 1 Register 9-3: WDTPSL: WDT Prescale Select Low Byte Register (Read Only) Register 9-4: WDTPSH: WDT Prescale Select High Byte Register (Read Only) Register 9-5: WDTTMR: WDT Timer Register (Read Only) TABLE 9-3: Summary of Registers Associated with Watchdog Timer TABLE 9-4: Summary of Configuration Word with Watchdog Timer 10.0 Flash Program Memory Control 10.1 PMADRL and PMADRH Registers 10.2 Flash Program Memory Overview TABLE 10-1: Flash Memory Organization by Device FIGURE 10-1: Flash Program Memory Read Flowchart FIGURE 10-2: Flash Program Memory Read Cycle Execution EXAMPLE 10-1: Flash Program Memory Read FIGURE 10-3: Flash Program Memory Unlock Sequence Flowchart FIGURE 10-4: Flash Program Memory Erase Flowchart EXAMPLE 10-2: Erasing One Row of Program Memory FIGURE 10-5: Block Writes to Flash Program Memory with 16 Write latches FIGURE 10-6: Flash Program Memory Write Flowchart EXAMPLE 10-3: Writing to Flash Program Memory (16 Write Latches) 10.3 Modifying Flash Program Memory FIGURE 10-7: Flash Program Memory Modify Flowchart 10.4 User ID, Device ID and Configuration Word Access TABLE 10-2: User ID, Device ID and Configuration Word Access (CFGS = 1) EXAMPLE 10-4: Configuration Word and Device ID Access 10.5 Write Verify FIGURE 10-8: Flash Program Memory Verify Flowchart 10.6 Register Definitions: Flash Program Memory Control Register 10-1: PMDATL: Program Memory Data Low Byte Register Register 10-2: PMDATH: Program Memory Data High Byte Register Register 10-3: PMADRL: Program Memory Address Low Byte Register Register 10-4: PMADRH: Program Memory Address High Byte Register Register 10-5: PMCON1: Program Memory Control 1 Register Register 10-6: PMCON2: Program Memory Control 2 Register TABLE 10-3: Summary of Registers Associated with Flash Program Memory TABLE 10-4: Summary of Configuration Word with Flash Program Memory 11.0 Cyclic Redundancy Check (CRC) Module 11.1 CRC Module Overview 11.2 CRC Functional Overview EXAMPLE 11-1: 11.3 CRC Polynomial Implementation EXAMPLE 11-2: CRC LFSR Example 11.4 CRC Data Sources 11.5 CRC Check Value 11.6 CRC Interrupt 11.7 Configuring the CRC 11.8 Program Memory Scan Configuration 11.9 Scanner Interrupt 11.10 Scanning Modes TABLE 11-1: Summary of Scanner Modes TABLE 11-2: Scan Interrupt Modes TABLE 11-3: ICD and Scanner Interactions 11.11 Register Definitions: CRC and Scanner Control Register 11-1: CRCCON0: CRC Control Register 0 Register 11-2: CRCCON1: CRC Control Register 1 Register 11-3: CRCDATH: CRC Data High Byte Register Register 11-4: CRCDATL: CRC Data Low Byte Register Register 11-5: CRCACCH: CRC Accumulator High Byte Register Register 11-6: CRCACCL: CRC Accumulator Low Byte Register Register 11-7: CRCSHIFTH: CRC Shift High Byte Register Register 11-8: CRCSHIFTL: CRC Shift Low Byte Register Register 11-9: CRCXORH: CRC XOR High Byte Register Register 11-10: CRCXORL: CRC XOR Low Byte Register Register 11-11: SCANCON0: Scanner Access Control Register 0 Register 11-12: SCANLADRH: SCAN Low Address High Byte Register Register 11-13: SCANLADRL: SCAN Low Address Low Byte Register Register 11-14: SCANHADRH: SCAN High Address High Byte Register Register 11-15: SCANHADRL: SCAN High Address Low Byte Register Register 11-16: SCANTRIG: SCAN Trigger Selection Register TABLE 11-4: Summary of Registers Associated with CRC 12.0 I/O Ports TABLE 12-1: Port Availability Per Device FIGURE 12-1: Generic I/O Port Operation 12.1 Alternate Pin Function 12.2 Register Definitions: Alternate Pin Function Control Register 12-1: APFCON: Alternate Pin Function Control Register 12.3 PORTA Registers EXAMPLE 12-1: Initializing PORTA TABLE 12-2: PORTA Output Priority (PIC12(L)F1612 only) TABLE 12-3: PORTA Output Priority (PIC16(L)F1613 only) 12.4 Register Definitions: PORTA Register 12-2: PORTA: PORTA Register Register 12-3: TRISA: PORTA Tri-State Register Register 12-4: LATA: PORTA Data Latch Register Register 12-5: ANSELA: PORTA Analog Select Register Register 12-6: WPUA: Weak Pull-Up PORTA Register Register 12-7: ODCONA: PORTA Open-Drain Control Register Register 12-8: SLRCONA: PORTA Slew Rate Control Register Register 12-9: INLVLA: PORTA Input Level Control Register TABLE 12-4: Summary of Registers Associated with PORTA TABLE 12-5: Summary of Configuration Word with PORTA 12.5 PORTC Registers (PIC16(L)F1613 only) TABLE 12-6: PORTC Output Priority 12.6 Register Definitions: PORTC (PIC16(L)F1613 ONLY) Register 12-10: PORTC: PORTC Register Register 12-11: TRISC: PORTC Tri-State Register Register 12-12: LATC: PORTC Data Latch Register Register 12-13: ANSELC: PORTC Analog Select Register Register 12-14: WPUC: Weak Pull-Up PORTC Register(1),(2) Register 12-15: ODCONC: PORTC Open-Drain Control Register Register 12-16: SLRCONC: PORTC Slew Rate Control Register Register 12-17: INLVLC: PORTC Input Level Control Register TABLE 12-7: Summary of Registers Associated with PORTC 13.0 Interrupt-On-Change 13.1 Enabling the Module 13.2 Individual Pin Configuration 13.3 Interrupt Flags 13.4 Clearing Interrupt Flags EXAMPLE 13-1: Clearing Interrupt Flags (PORTA Example) 13.5 Operation in Sleep FIGURE 13-1: Interrupt-On-Change Block Diagram (PORTA Example) 13.6 Register Definitions: Interrupt-on-Change Control Register 13-1: IOCAP: Interrupt-on-Change PORTA Positive Edge Register Register 13-2: IOCAN: Interrupt-on-Change PORTA Negative Edge Register Register 13-3: IOCAF: Interrupt-on-Change PORTA Flag Register Register 13-4: IOCCP: Interrupt-on-Change PORTC Positive Edge Register(1) Register 13-5: IOCCN: Interrupt-on-Change PORTC Negative Edge Register(1) Register 13-6: IOCCF: Interrupt-on-Change PORTC Flag Register(1) TABLE 13-1: Summary of Registers Associated with Interrupt-on-Change 14.0 Fixed Voltage Reference (FVR) 14.1 Independent Gain Amplifier 14.2 FVR Stabilization Period FIGURE 14-1: Voltage Reference Block Diagram TABLE 14-1: Peripherals Requiring the Fixed Voltage Reference (FVR) 14.3 Register Definitions: FVR Control Register 14-1: FVRCON: Fixed Voltage Reference Control Register TABLE 14-2: Summary of Registers Associated with the Fixed Voltage Reference 15.0 Temperature Indicator Module 15.1 Circuit Operation EQUATION 15-1: Vout Ranges FIGURE 15-1: Temperature Circuit Diagram 15.2 Minimum Operating Vdd TABLE 15-1: Recommended Vdd vs. Range 15.3 Temperature Output 15.4 ADC Acquisition Time TABLE 15-2: Summary of Registers Associated with the Temperature Indicator 16.0 Analog-to-Digital Converter (ADC) Module FIGURE 16-1: ADC Block Diagram 16.1 ADC Configuration TABLE 16-1: ADC Clock Period (Tad) Vs. Device Operating Frequencies FIGURE 16-2: Analog-to-Digital Conversion Tad Cycles FIGURE 16-3: 10-Bit ADC Conversion Result Format 16.2 ADC Operation TABLE 16-2: Auto-Conversion Sources EXAMPLE 16-1: ADC Conversion 16.3 Register Definitions: ADC Control Register 16-1: ADCON0: ADC Control Register 0 Register 16-2: ADCON1: ADC Control Register 1 Register 16-3: ADCON2: ADC Control Register 2 Register 16-4: ADRESH: ADC Result Register High (ADRESH) ADFM = 0 Register 16-5: ADRESL: ADC Result Register Low (ADRESL) ADFM = 0 Register 16-6: ADRESH: ADC Result Register High (ADRESH) ADFM = 1 Register 16-7: ADRESL: ADC Result Register Low (ADRESL) ADFM = 1 16.4 ADC Acquisition Requirements EQUATION 16-1: Acquisition Time Example FIGURE 16-4: Analog Input Model FIGURE 16-5: ADC Transfer Function TABLE 16-3: Summary of Registers Associated with ADC 17.0 8-bit Digital-to-Analog Converter (DAC1) Module 17.1 Output Voltage Selection EQUATION 17-1: DAC Output Voltage 17.2 Ratiometric Output Level 17.3 DAC Voltage Reference Output FIGURE 17-1: Digital-to-Analog Converter Block Diagram FIGURE 17-2: Voltage Reference Output Buffer Example 17.4 Operation During Sleep 17.5 Effects of a Reset 17.6 Register Definitions: DAC Control Register 17-1: DAC1CON0: DAC1 Control Register 0 Register 17-2: DAC1CON1: DAC1 Control Register 1 TABLE 17-1: Summary of Registers Associated with the DAC1 Module 18.0 Comparator Module 18.1 Comparator Overview TABLE 18-1: Comparator Availability Per Device FIGURE 18-1: Single Comparator FIGURE 18-2: Comparator Module Simplified Block Diagram 18.2 Comparator Control TABLE 18-2: Comparator Output State vs. Input Conditions 18.3 Comparator Hysteresis 18.4 Timer1 Gate Operation 18.5 Comparator Interrupt 18.6 Comparator Positive Input Selection 18.7 Comparator Negative Input Selection 18.8 Comparator Response Time 18.9 Analog Input Connection Considerations FIGURE 18-3: Analog Input Model 18.10 Register Definitions: Comparator Control Register 18-1: CMxCON0: Comparator Cx Control Register 0 Register 18-2: CMxCON1: Comparator Cx Control Register 1 Register 18-3: CMOUT: Comparator Output Register TABLE 18-3: Summary of Registers Associated with Comparator Module 19.0 Zero-Cross Detection (ZCD) Module 19.1 External Resistor Selection EQUATION 19-1: External Resistor FIGURE 19-1: External Voltage FIGURE 19-2: Simplified ZCD Block Diagram 19.2 ZCD Logic Output 19.3 ZCD Logic Polarity 19.4 ZCD Interrupts 19.5 Correcting for Vcpinv offset EQUATION 19-2: ZCD Event Offset EQUATION 19-3: ZCD Pull-up/down EQUATION 19-4: 19.6 Handling Vpeak variations EQUATION 19-5: Series R for V range 19.7 Operation During Sleep 19.8 Effects of a Reset 19.9 Register Definitions: ZCD Control Register 19-1: ZCDxCON: Zero-Cross Detection Control Register TABLE 19-1: Summary of Registers Associated with the ZCD Module TABLE 19-2: Summary of Configuration Word with the ZCD Module 20.0 Timer0 Module 20.1 Timer0 Operation FIGURE 20-1: Timer0 Block Diagram 20.2 Register Definitions: Option Register Register 20-1: OPTION_REG: OPTION Register TABLE 20-1: Summary of Registers Associated with Timer0 21.0 Timer1/3/5 Module with Gate Control FIGURE 21-1: Timer1 Block Diagram 21.1 Timer1 Operation TABLE 21-1: Timer1 Enable Selections 21.2 Clock Source Selection TABLE 21-2: Clock Source Selections 21.3 Timer1 Prescaler 21.4 Timer1 Operation in Asynchronous Counter Mode 21.5 Timer1 Gate TABLE 21-3: Timer1 Gate Enable Selections TABLE 21-4: Timer1 Gate Sources 21.6 Timer1 Interrupt 21.7 Timer1 Operation During Sleep FIGURE 21-2: Timer1 Incrementing Edge FIGURE 21-3: Timer1 Gate Enable Mode FIGURE 21-4: Timer1 Gate Toggle Mode FIGURE 21-5: Timer1 Gate Single-Pulse Mode FIGURE 21-6: Timer1 Gate Single-Pulse and Toggle Combined Mode 21.8 Register Definitions: Timer1 Control Register 21-1: T1CON: Timer1 Control Register Register 21-2: T1GCON: Timer1 Gate Control Register TABLE 21-5: Summary of Registers Associated with Timer1 22.0 Timer2/4/6 Module FIGURE 22-1: Timer2 with Hardware Limit Timer (HLT) Block Diagram FIGURE 22-2: Timer2 Clock Source Block Diagram 22.1 Timer2 Operation 22.2 Timer2 Interrupt FIGURE 22-3: Timer2 Prescaler, Postscaler, and Interrupt Timing Diagram 22.3 Timer2 Output 22.4 External Reset Sources 22.5 Operation Examples TABLE 22-1: Timer2 Operating Modes FIGURE 22-4: Software Gate Mode Timing Diagram FIGURE 22-5: Hardware Gate Mode Timing Diagram FIGURE 22-6: Edge-Triggered Hardware Limit Mode Timing Diagram FIGURE 22-7: Level-Triggered Hardware Limit Timing Diagram FIGURE 22-8: Software Start One-Shot Mode Timing Diagram FIGURE 22-9: Edge-Triggered One-Shot Mode Timing Diagram FIGURE 22-10: Edge-Triggered Hardware Limit One-Shot Timing Diagram 22.6 Timer2 Operation During Sleep FIGURE 22-11: Level-Triggered Hardware Limit One-Shot Mode Timing Diagram 22.7 Register Definitions: Timer2/4/6 Control TABLE 22-2: Register 22-1: TxCLKCON: Timerx Clock Selection Register Register 22-2: TxCON: Timerx Control Register Register 22-3: TxHLT: Timerx Clock Selection Register Register 22-4: TxRST: Timer2 External Reset Signal Selection Register TABLE 22-3: External Reset Sources TABLE 22-4: Summary of Registers Associated with Timer2 23.0 Capture/Compare/PWM Modules 23.1 Capture Mode FIGURE 23-1: Capture Mode Operation Block Diagram 23.2 Compare Mode FIGURE 23-2: Compare Mode Operation Block Diagram 23.3 PWM Overview FIGURE 23-3: Simplified PWM Block Diagram 23.4 CCP/PWM Clock Selection EQUATION 23-1: PWM Period EQUATION 23-2: Pulse Width EQUATION 23-3: Duty Cycle Ratio FIGURE 23-4: ccpX Duty-Cycle Alignment EQUATION 23-4: PWM Resolution TABLE 23-1: Example PWM Frequencies and Resolutions (Fosc = 20 MHz) TABLE 23-2: Example PWM Frequencies and Resolutions (Fosc = 8 MHz) 23.5 Register Definitions: CCP Control Register 23-1: CCPxCON: CCPx Control Register Register 23-2: CCPTMRS: PWM Timer Selection Control Register 0 Register 23-3: CCPRxL: CCPx Low Byte Register Register 23-4: CCPRxH: CCPx High Byte Register Register 23-5: CCPxCAP: CCPx Capture Input Selection Register TABLE 23-3: Summary of Registers Associated with Standard PWM 24.0 Complementary Waveform Generator (CWG) Module 24.1 Fundamental Operation FIGURE 24-1: Simplified CWG Block Diagram (Half Bridge Mode) FIGURE 24-2: Simplified CWG Block Diagram (Push-Pull Mode) FIGURE 24-3: Simplified CWG Block Diagram (Forward and Reverse Full-Bridge Modes) FIGURE 24-4: Simplified CWG Block Diagram (Output Steering Modes) 24.2 Clock Source 24.3 Selectable Input Sources TABLE 24-1: Selectable Input Sources 24.4 Output Control FIGURE 24-5: CWG Output Block Diagram 24.5 Dead-Band Control 24.6 Rising Edge and Reverse Dead Band 24.7 Falling Edge and Forward Dead Band FIGURE 24-6: Dead-Band Operation CWGxDBR = 0x01, CWGxDBF = 0x02 FIGURE 24-7: Dead-Band Operation, CWGxDBR = 0x03, CWGxDBF = 0x04, Source Shorter Than Dead Band 24.8 Dead-Band Uncertainty EQUATION 24-1: Dead-Band Uncertainty FIGURE 24-8: Example of PWM Direction Change FIGURE 24-9: CWG Half-Bridge Mode Operation 24.9 CWG Steering Mode FIGURE 24-10: Example of Steering Event at End of Instruction (MODE<2:0> = 000) FIGURE 24-11: Example of Steering Event at Beginning of Instruction (MODE<2:0> = 001) 24.10 Auto-Shutdown 24.11 Operation During Sleep FIGURE 24-12: CWG Shutdown Block Diagram 24.12 Configuring the CWG FIGURE 24-13: Shutdown Functionality, Auto-Restart Disabled (REN = 0, LSAC = 01, LSBD = 01) FIGURE 24-14: Shutdown Functionality, Auto-Restart Enabled (REN = 1, LSAC = 01, LSBD = 01) 24.13 Register Definitions: CWG Control Register 24-1: CWGxCON0: CWGX Control Register 0 Register 24-2: CWGxCON1: CWGX Control Register 1 Register 24-3: CWGxDBR: CWGX Rising Dead-Band Counter Register Register 24-4: CWGxDBF: CWGX Falling Dead-Band Counter Register Register 24-5: CWGxAS0: CWGX Auto-Shutdown Control Register 0 Register 24-6: CWGxAS1: CWGX Auto-Shutdown Control Register 1 Register 24-7: CWGxOCON0: CWGX Steering Control Register 0(1) Register 24-8: CWGxOCON1: CWGX Output Enable Register 1 Register 24-9: CWGxCLKCON: CWGX Clock Selection Control Register Register 24-10: CWGxISM: CWGX Input Selection Register TABLE 24-2: Summary of Registers Associated with CWG 25.0 Signal Measurement Timer (SMT) FIGURE 25-1: SMTx Block Diagram FIGURE 25-2: SMTx Signal and Window Block Diagram 25.1 SMT Operation 25.2 Basic Timer Function Registers 25.3 Halt Operation 25.4 Polarity Control 25.5 Status Information 25.6 Modes of Operation TABLE 25-1: Modes of Operation FIGURE 25-3: Timer Mode Timing Diagram FIGURE 25-4: Gated Timer Mode Repeat Acquisition Timing Diagram FIGURE 25-5: Gated Timer Mode Single Acquisition Timing Diagram FIGURE 25-6: Period And Duty-Cycle Repeat Acquisition Mode Timing Diagram FIGURE 25-7: Period And Duty-Cycle Single Acquisition Timing Diagram FIGURE 25-8: High and Low Measure Mode Repeat Acquisition Timing Diagram FIGURE 25-9: High and Low Measure Mode Single Acquisition Timing Diagram FIGURE 25-10: Windowed Measure Mode Repeat Acquisition Timing Diagram FIGURE 25-11: Windowed Measure Mode Single Acquisition Timing Diagram FIGURE 25-12: Gated Windowed Measure Mode Repeat Acquisition Timing Diagram FIGURE 25-13: Gated Windowed Measure Mode Single Acquisition Timing Diagrams FIGURE 25-14: Time Of Flight Mode Repeat Acquisition Timing Diagram FIGURE 25-15: Time Of Flight Mode Single Acquisition Timing Diagram FIGURE 25-16: Capture Mode Repeat Acquisition Timing Diagram FIGURE 25-17: Capture Mode Single Acquisition Timing Diagram FIGURE 25-18: Counter Mode Timing Diagram FIGURE 25-19: Gated Counter Mode Repeat Acquisition Timing Diagram FIGURE 25-20: Gated Counter Mode Single Acquisition Timing Diagram FIGURE 25-21: Windowed Counter Mode Repeat Acquisition Timing Diagram FIGURE 25-22: Windowed Counter Mode Single Acquisition Timing Diagram 25.7 Interrupts 25.8 Register Definitions: SMT Control TABLE 25-2: Register 25-1: SMTxCON0: SMT Control Register 0 Register 25-2: SMTxCON1: SMT Control Register 1 Register 25-3: SMTxSTAT: SMT Status Register Register 25-4: SMTxCLK: SMT Clock Selection Register Register 25-5: SMTxWIN: SMTx Window Input Select Register Register 25-6: SMT1SIG: SMT1 Signal Input Select Register Register 25-7: SMTxTMRL: SMT Timer Register – Low Byte Register 25-8: SMTxTMRH: SMT Timer Register – High Byte Register 25-9: SMTxTMRU: SMT Timer Register – Upper Byte Register 25-10: SMTxCPRL: SMT Captured Period Register – Low Byte Register 25-11: SMTxCPRH: SMT Captured Period Register – High Byte Register 25-12: SMTxCPRU: SMT Captured Period Register – Upper Byte Register 25-13: SMTxCPWL: SMT Captured Pulse Width Register – Low Byte Register 25-14: SMTxCPWH: SMT Captured Pulse Width Register – High Byte Register 25-15: SMTxCPWU: SMT Captured Pulse Width Register – Upper Byte Register 25-16: SMTxPRL: SMT Period Register – Low Byte Register 25-17: SMTxPRH: SMT Period Register – High Byte Register 25-18: SMTxPRU: SMT Period Register – Upper Byte TABLE 25-3: Summary of Registers Associated with SMTx 26.0 In-Circuit Serial Programming™ (ICSP™) 26.1 High-Voltage Programming Entry Mode 26.2 Low-Voltage Programming Entry Mode 26.3 Common Programming Interfaces FIGURE 26-1: ICD RJ-11 Style Connector Interface FIGURE 26-2: PICkit™ Programmer Style Connector Interface FIGURE 26-3: Typical connection for ICSP™ Programming 27.0 Instruction Set Summary 27.1 Read-Modify-Write Operations TABLE 27-1: Opcode Field Descriptions TABLE 27-2: Abbreviation Descriptions FIGURE 27-1: General Format for Instructions TABLE 27-3: Enhanced Mid-Range Instruction Set TABLE 27-3: Enhanced Mid-Range Instruction Set (Continued) 27.2 Instruction Descriptions 28.0 Electrical Specifications 28.1 Absolute Maximum Ratings(†) 28.2 Standard Operating Conditions FIGURE 28-1: Voltage Frequency Graph, -40°C £ Ta £ +125°C, PIC12F1612/16F1613 only FIGURE 28-2: Voltage Frequency Graph, -40°C £ Ta £ +125°C, PIC12LF1612/16F1613 only 28.3 DC Characteristics TABLE 28-1: Supply Voltage FIGURE 28-3: POR and POR Rearm with Slow Rising Vdd TABLE 28-2: Supply Current (Idd)(1,2) TABLE 28-3: Power-Down Currents (Ipd)(1,2) TABLE 28-4: I/O Ports TABLE 28-5: Memory Programming Specifications TABLE 28-6: Thermal Characteristics 28.4 AC Characteristics FIGURE 28-4: Load Conditions FIGURE 28-5: Clock Timing TABLE 28-7: Clock Oscillator Timing Requirements TABLE 28-8: Oscillator Parameters FIGURE 28-6: HFINTOSC Frequency Accuracy Over Vdd and Temperature TABLE 28-9: PLL Clock Timing Specifications FIGURE 28-7: CLKOUT and I/O Timing TABLE 28-10: CLKOUT and I/O Timing Parameters FIGURE 28-8: Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Timing TABLE 28-11: Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer and Brown-Out Reset Parameters FIGURE 28-9: Brown-Out Reset Timing and Characteristics FIGURE 28-10: Timer0 and Timer1 External Clock Timings TABLE 28-12: Timer0 and Timer1 External Clock Requirements TABLE 28-13: Analog-to-Digital Converter (ADC) Characteristics(1,2,3) FIGURE 28-11: ADC Conversion Timing (ADC Clock Fosc-based) FIGURE 28-12: ADC Conversion Timing (ADC Clock from FRC) TABLE 28-14: ADC Conversion Requirements TABLE 28-15: Comparator Specifications(1) TABLE 28-16: Digital-to-Analog Converter (DAC) Specifications(1) TABLE 28-17: Zero Cross Pin Specifications 29.0 DC and AC Characteristics Graphs and Charts 30.0 Development Support 30.1 MPLAB X Integrated Development Environment Software 30.2 MPLAB XC Compilers 30.3 MPASM Assembler 30.4 MPLINK Object Linker/ MPLIB Object Librarian 30.5 MPLAB Assembler, Linker and Librarian for Various Device Families 30.6 MPLAB X SIM Software Simulator 30.7 MPLAB REAL ICE In-Circuit Emulator System 30.8 MPLAB ICD 3 In-Circuit Debugger System 30.9 PICkit 3 In-Circuit Debugger/ Programmer 30.10 MPLAB PM3 Device Programmer 30.11 Demonstration/Development Boards, Evaluation Kits, and Starter Kits 30.12 Third-Party Development Tools 31.0 Packaging Information 31.1 Package Marking Information 31.1 Package Marking Information (Continued) TABLE 31-1: 8-Lead 3X3 DFN (MF) Top Marking 31.2 Package Details Appendix A: Data Sheet Revision History Product ID System Trademarks Worldwide Sales and Service