Datasheet dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X, PIC24EPXXXGP/MC20X (Microchip) - 5

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dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X Pin Diagrams 28-Pin SPDIP/SOIC/SSOP(1,2)
= Pins are up to 5V tolerant MCLR 1 28 AVDD AN0/OA2OUT/RA0 2 27 AVSS AN1/C2IN1+/RA1 3 26 RPI47/T5CK/RB15 PGED3/VREF-/AN2/C2IN1-/SS1/RPI32/CTED2/RB0 4 25 RPI46/T3CK/RB14
2 2
PGEC3/VREF+/AN3/OA1OUT/RPI33/CTED1/RB1 5
50 0
24 RPI45/CTPLS/RB13
P 2
PGEC1/AN4/C1IN1+/RPI34/RB2 6
G
23 RPI44/RB12
X GP
PGED1/AN5/C1IN1-/RP35/RB3 7
X
22 TDI/RP43/RB11
X XX
VSS 8
PX
21 TDO/RP42/RB10
E
OSC1/CLKI/RA2 9
4
20 VCAP
C33EP 2
OSC2/CLKO/RA3 10
PI IC
19 VSS
s P
RP36/RB4 11
d
18 TMS/ASDA1/SDI1/RP41/RB9
(3)
CVREF2O/RP20/T1CK/RA4 12 17 TCK/CVREF1O/ASCL1/SDO1/RP40/T4CK/RB8 VDD 13 16 SCK1/RP39/INT0/RB7 PGED2/ASDA2/RP37/RB5 14 15 PGEC2/ASCL2/RP38/RB6 MCLR 1 28 AVDD AN0/OA2OUT/RA0 2 27 AVSS AN1/C2IN1+/RA1 3 26 RPI47/PWM1L/T5CK/RB15 PGED3/VREF-/AN2/C2IN1-/SS1/RPI32/CTED2/RB0 4 25 RPI46/PWM1H/T3CK/RB14
502
PGEC3/VREF+/AN3/OA1OUT/RPI33/CTED1/RB1 5 24 RPI45/PWM2L/CTPLS/RB13
202
PGEC1/AN4/C1IN1+/RPI34/RB2 6
C
23 RPI44/PWM2H/RB12
C202/ M
PGED1/AN5/C1IN1-/RP35/RB3 7
X
22 TDI/RP43/PWM3L/RB11
XM X
VSS 8
X
21 TDO/RP42/PWM3H/RB10
PXX
OSC1/CLKI/RA2 9 20 VCAP OSC2/CLKO/RA3 10
C24EP
19 VSS
C33E PI
FLT32/RP36/RB4 11
PI
18 TMS/ASDA1/SDI1/RP41/RB9
(3) s d
CVREF2O/RP20/T1CK/RA4 12 17 TCK/CVREF1O/ASCL1/SDO1/RP40/T4CK/RB8 VDD 13 16 SCK1/RP39/INT0/RB7 PGED2/ASDA2/RP37/RB5 14 15 PGEC2/ASCL2/RP38/RB6
Note 1:
The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See
Section 11.4 “Peripheral Pin Select (PPS)”
for available peripherals and for information on limitations.
2:
Every I/O port pin (RAx-RGx) can be used as a Change Notification pin (CNAx-CNGx). See
Section 11.0 “I/O Ports”
for more information.
3:
There is an internal pull-up resistor connected to the TMS pin when the JTAG interface is active. See the JTAGEN bit field in Table 27-2.  2011-2013 Microchip Technology Inc. DS70000657H-page 5 Document Outline Operating Conditions Core: 16-Bit dsPIC33E/PIC24E CPU Clock Management Power Management High-Speed PWM Advanced Analog Features Timers/Output Compare/Input Capture Communication Interfaces Direct Memory Access (DMA) Input/Output Qualification and Class B Support Debugger Development Support dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X Product Families TABLE 1: dsPIC33EPXXXGP50X and PIC24EPXXXGP20X General Purpose Families TABLE 2: dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X Motor Control Families Pin Diagrams Pin Diagrams (Continued) Pin Diagrams (Continued) Pin Diagrams (Continued) Pin Diagrams (Continued) Pin Diagrams (Continued) Pin Diagrams (Continued) Pin Diagrams (Continued) Pin Diagrams (Continued) Pin Diagrams (Continued) Pin Diagrams (Continued) Pin Diagrams (Continued) Pin Diagrams (Continued) Pin Diagrams (Continued) Pin Diagrams (Continued) Pin Diagrams (Continued) Pin Diagrams (Continued) Table of Contents Most Current Data Sheet Errata Customer Notification System Referenced Sources 1.0 Device Overview FIGURE 1-1: dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X Block Diagram TABLE 1-1: Pinout I/O Descriptions 2.0 Guidelines for Getting Started with 16-bit Digital Signal Controllers and Microcontrollers 2.1 Basic Connection Requirements 2.2 Decoupling Capacitors FIGURE 2-1: Recommended Minimum connection 2.3 CPU Logic Filter Capacitor Connection (Vcap) 2.4 Master Clear (MCLR) Pin FIGURE 2-2: Example of MCLR Pin Connections 2.5 ICSP Pins 2.6 External Oscillator Pins FIGURE 2-3: Suggested Placement of the Oscillator Circuit 2.7 Oscillator Value Conditions on Device Start-up 2.8 Unused I/Os 2.9 Application Examples FIGURE 2-4: Boost Converter Implementation FIGURE 2-5: Single-Phase Synchronous Buck converter FIGURE 2-6: Multiphase Synchronous Buck converter FIGURE 2-7: Interleaved PFC FIGURE 2-8: BEMF voltage measured using the ADC Module 3.0 CPU 3.1 Registers 3.2 Instruction Set 3.3 Data Space Addressing 3.4 Addressing Modes FIGURE 3-1: dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X CPU Block Diagram 3.5 Programmer’s Model TABLE 3-1: Programmer’s Model Register Descriptions FIGURE 3-2: Programmer’s Model 3.6 CPU Resources 3.7 CPU Control Registers Register 3-1: SR: CPU Status Register Register 3-2: CORCON: Core Control Register 3.8 Arithmetic Logic Unit (ALU) 3.9 DSP Engine (dsPIC33EPXXXMC20X/50X and dsPIC33EPXXXGP50X Devices Only) TABLE 3-2: DSP Instructions Summary 4.0 Memory Organization 4.1 Program Address Space FIGURE 4-1: Program Memory Map for dsPIC33EP32GP50X, dsPIC33EP32MC20X/50X and PIC24EP32GP/MC20X Devices FIGURE 4-2: Program Memory Map for dsPIC33EP64GP50X, dsPIC33EP64MC20X/50X and PIC24EP64GP/MC20X Devices FIGURE 4-3: Program Memory Map for dsPIC33EP128GP50X, dsPIC33EP128MC20X/50X and PIC24EP128GP/MC20X Devices FIGURE 4-4: Program Memory Map for dsPIC33EP256GP50X, dsPIC33EP256MC20X/50X and PIC24EP256GP/MC20X Devices FIGURE 4-5: Program Memory Map for dsPIC33EP512GP50X, dsPIC33EP512MC20X/50X and PIC24EP512GP/MC20X Devices FIGURE 4-6: Program Memory Organization 4.2 Data Address Space FIGURE 4-7: Data Memory Map for dsPIC33EP32MC20X/50X and dsPIC33EP32GP50X Devices FIGURE 4-8: Data Memory Map for dsPIC33EP64MC20X/50X and dsPIC33EP64GP50X Devices FIGURE 4-9: Data Memory Map for dsPIC33EP128MC20X/50X and dsPIC33EP128GP50X Devices FIGURE 4-10: Data Memory Map for dsPIC33EP256MC20X/50X and dsPIC33EP256GP50X Devices FIGURE 4-11: Data Memory Map for dsPIC33EP512MC20X/50X and dsPIC33EP512GP50X Devices FIGURE 4-12: Data Memory Map for PIC24EP32GP/MC20X/50X Devices FIGURE 4-13: Data Memory Map for PIC24EP64GP/MC20X/50X Devices FIGURE 4-14: Data Memory Map for PIC24EP128GP/MC20X/50X Devices FIGURE 4-15: Data Memory Map for PIC24EP256GP/MC20X/50X Devices FIGURE 4-16: Data Memory Map for PIC24EP512GP/MC20X/50X Devices 4.3 Memory Resources 4.4 Special Function Register Maps TABLE 4-1: CPU Core Register Map for dsPIC33EPXXXMC20X/50X and dsPIC33EPXXXGP50X Devices Only TABLE 4-2: CPU Core Register Map for PIC24EPXXXGP/MC20X Devices Only TABLE 4-3: Interrupt Controller Register Map for PIC24EPXXXGP20X Devices Only TABLE 4-4: Interrupt Controller Register Map for PIC24EPXXXMC20X Devices Only TABLE 4-5: Interrupt Controller Register Map for dsPIC33EPXXXGP50X Devices Only TABLE 4-6: Interrupt Controller Register Map for dsPIC33EPXXXMC20X Devices Only TABLE 4-7: Interrupt Controller Register Map for dsPIC33EPXXXMC50X Devices Only TABLE 4-8: Timer1 through Timer5 Register Map TABLE 4-9: Input Capture 1 through Input Capture 4 Register Map TABLE 4-10: Output Compare 1 through Output Compare 4 Register Map TABLE 4-11: PTG Register Map TABLE 4-12: PWM Register Map for dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X Devices Only TABLE 4-13: PWM Generator 1 Register Map for dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X Devices Only TABLE 4-14: PWM Generator 2 Register Map for dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X Devices Only TABLE 4-15: PWM Generator 3 Register Map for dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X Devices Only TABLE 4-16: QEI1 Register Map for dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X Devices Only TABLE 4-17: I2C1 and I2C2 Register Map TABLE 4-18: UART1 and UART2 Register Map TABLE 4-19: SPI1 and SPI2 Register Map TABLE 4-20: ADC1 Register Map TABLE 4-21: ECAN1 Register Map When WIN (C1CTRL1<0>) = 0 or 1 FOR dsPIC33EPXXXMC/GP50X Devices Only TABLE 4-22: ECAN1 Register Map When WIN (C1CTRL1<0>) = 0 For dsPIC33EPXXXMC/GP50X Devices Only TABLE 4-23: ECAN1 Register Map When WIN (C1CTRL1<0>) = 1 For dsPIC33EPXXXMC/GP50X Devices Only TABLE 4-24: CRC Register Map TABLE 4-25: Peripheral Pin Select Output Register Map for dsPIC33EPXXXGP/MC202/502 and PIC24EPXXXGP/MC202 Devices Only TABLE 4-26: Peripheral Pin Select Output Register Map for dsPIC33EPXXXGP/MC203/503 and PIC24EPXXXGP/MC203 Devices Only TABLE 4-27: Peripheral Pin Select Output Register Map for dsPIC33EPXXXGP/MC204/504 and PIC24EPXXXGP/MC204 Devices Only TABLE 4-28: Peripheral Pin Select Output Register Map for dsPIC33EPXXXGP/MC206/506 and PIC24EPXXXGP/MC206 Devices Only TABLE 4-29: Peripheral Pin Select Input Register Map for PIC24EPXXXMC20X Devices Only TABLE 4-30: Peripheral Pin Select Input Register Map for PIC24EPXXXGP20X Devices Only TABLE 4-31: Peripheral Pin Select Input Register Map for dsPIC33EPXXXGP50X Devices Only TABLE 4-32: Peripheral Pin Select Input Register Map for dsPIC33EPXXXMC50X Devices Only TABLE 4-33: Peripheral Pin Select Input Register Map for dsPIC33EPXXXMC20X Devices Only TABLE 4-34: NVM Register Map TABLE 4-35: System Control Register Map TABLE 4-36: Reference Clock Register Map TABLE 4-37: PMD Register Map for PIC24EPXXXGP20X Devices Only TABLE 4-38: PMD Register Map for PIC24EPXXXMC20X Devices Only TABLE 4-39: PMD Register Map for dsPIC33EPXXXGP50X Devices Only TABLE 4-40: PMD Register Map for dsPIC33EPXXXMC50X Devices Only TABLE 4-41: PMD Register Map for dsPIC33EPXXXMC20X Devices Only TABLE 4-42: Op Amp/Comparator Register Map TABLE 4-43: CTMU Register Map TABLE 4-44: JTAG INTERFACE Register Map TABLE 4-45: DMAC Register Map TABLE 4-46: PORTA Register Map For PIC24EPXXXGP/MC206 and dsPIC33EPXXXGP/MC206/506 Devices Only TABLE 4-47: PORTB Register Map For PIC24EPXXXGP/MC206 and dsPIC33EPXXXGP/MC206/506 Devices Only TABLE 4-48: PORTC Register Map For PIC24EPXXXGP/MC206 and dsPIC33EPXXXGP/MC206/506 Devices Only TABLE 4-49: PORTD Register Map For PIC24EPXXXGP/MC206 and dsPIC33EPXXXGP/MC206/506 Devices Only TABLE 4-50: PORTE Register Map For PIC24EPXXXGP/MC206 and dsPIC33EPXXXGP/MC206/506 Devices Only TABLE 4-51: PORTF Register Map For PIC24EPXXXGP/MC206 and dsPIC33EPXXXGP/MC206/506 Devices Only TABLE 4-52: PORTG Register Map For PIC24EPXXXGP/MC206 and dsPIC33EPXXXGP/MC206/506 Devices Only TABLE 4-53: PORTA Register Map For PIC24EPXXXGP/MC204 and dsPIC33EPXXXGP/MC204/504 Devices Only TABLE 4-54: PORTB Register Map For PIC24EPXXXGP/MC204 and dsPIC33EPXXXGP/MC204/504 Devices Only TABLE 4-55: PORTC Register Map For PIC24EPXXXGP/MC204 and dsPIC33EPXXXGP/MC204/504 Devices Only TABLE 4-56: PORTA Register Map For PIC24EPXXXGP/MC203 and dsPIC33EPXXXGP/MC203/503 Devices Only TABLE 4-57: PORTB Register Map For PIC24EPXXXGP/MC203 and dsPIC33EPXXXGP/MC203/503 Devices Only TABLE 4-58: PORTC Register Map For PIC24EPXXXGP/MC203 and dsPIC33EPXXXGP/MC203/503 Devices Only TABLE 4-59: PORTA Register Map For PIC24EPXXXGP/MC202 and dsPIC33EPXXXGP/MC202/502 Devices Only TABLE 4-60: PORTB Register Map For PIC24EPXXXGP/MC202 and dsPIC33EPXXXGP/MC202/502 Devices Only EXAMPLE 4-1: Extended Data Space (EDS) Read Address Generation EXAMPLE 4-2: Extended Data Space (EDS) Write Address Generation EXAMPLE 4-3: Paged Data Memory Space TABLE 4-61: Overflow and Underflow Scenarios at Page 0, EDS and PSV Space Boundaries(2,3,4) FIGURE 4-17: EDS Memory Map TABLE 4-62: Data Memory Bus Arbiter Priority FIGURE 4-18: Arbiter Architecture FIGURE 4-19: CALL Stack Frame 4.5 Instruction Addressing Modes TABLE 4-63: Fundamental Addressing Modes Supported 4.6 Modulo Addressing (dsPIC33EPXXXMC20X/50X and dsPIC33EPXXXGP50X Devices Only) FIGURE 4-20: Modulo Addressing Operation Example 4.7 Bit-Reversed Addressing (dsPIC33EPXXXMC20X/50X and dsPIC33EPXXXGP50X Devices Only) FIGURE 4-21: Bit-Reversed Addressing Example TABLE 4-64: Bit-Reversed Addressing Sequence (16-Entry) 4.8 Interfacing Program and Data Memory Spaces TABLE 4-65: Program Space Address Construction FIGURE 4-22: Data Access from Program Space Address Generation FIGURE 4-23: Accessing Program Memory with Table Instructions 5.0 Flash Program Memory 5.1 Table Instructions and Flash Programming FIGURE 5-1: Addressing for Table Registers 5.2 RTSP Operation 5.3 Programming Operations 5.4 Flash Memory Resources 5.5 Control Registers Register 5-1: NVMCON: Nonvolatile Memory (NVM) Control Register Register 5-2: NVMADRH: Nonvolatile Memory Address Register High Register 5-3: NVMADRL: Nonvolatile Memory Address Register Low Register 5-4: NVMKEY: Nonvolatile Memory Key 6.0 Resets FIGURE 6-1: Reset System Block Diagram 6.1 Reset Resources Register 6-1: RCON: Reset Control Register(1) 7.0 Interrupt Controller 7.1 Interrupt Vector Table 7.2 Reset Sequence FIGURE 7-1: dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X Interrupt Vector Table TABLE 7-1: Interrupt Vector Details 7.3 Interrupt Resources 7.4 Interrupt Control and Status Registers Register 7-1: SR: CPU Status Register(1) Register 7-2: CORCON: Core Control Register(1) Register 7-3: INTCON1: Interrupt Control Register 1 Register 7-4: INTCON2: Interrupt Control Register 2 Register 7-5: INTCON3: Interrupt Control Register 3 Register 7-6: INTCON4: Interrupt Control Register 4 Register 7-7: INTTREG: Interrupt Control and Status Register 8.0 Direct Memory Access (DMA) FIGURE 8-1: DMA Controller Module TABLE 8-1: DMA Channel to Peripheral Associations FIGURE 8-2: DMA Controller Block Diagram 8.1 DMA Resources 8.2 DMAC Registers Register 8-1: DMAxCON: DMA Channel x Control Register Register 8-2: DMAxREQ: DMA Channel x IRQ Select Register Register 8-3: DMAxSTAH: DMA Channel x Start Address Register A (High) Register 8-4: DMAxSTAL: DMA Channel x Start Address Register A (Low) Register 8-5: DMAxSTBH: DMA Channel x Start Address Register B (High) Register 8-6: DMAxSTBL: DMA Channel x Start Address Register B (Low) Register 8-7: DMAxPAD: DMA Channel x Peripheral Address Register(1) Register 8-8: DMAxCNT: DMA Channel x Transfer Count Register(1) Register 8-9: DSADRH: DMA Most Recent RAM High Address Register Register 8-10: DSADRL: DMA Most Recent RAM Low Address Register Register 8-11: DMAPWC: DMA Peripheral Write Collision Status Register Register 8-12: DMARQC: DMA Request Collision Status Register Register 8-13: DMALCA: DMA Last Channel Active Status Register Register 8-14: DMAPPS: DMA Ping-Pong Status Register 9.0 Oscillator Configuration FIGURE 9-1: Oscillator System Diagram 9.1 CPU Clocking System EQUATION 9-1: Device Operating Frequency FIGURE 9-2: PLL Block Diagram EQUATION 9-2: Fpllo Calculation EQUATION 9-3: Fvco Calculation TABLE 9-1: Configuration Bit Values for Clock Selection 9.2 Oscillator Resources 9.3 Oscillator Control Registers Register 9-1: OSCCON: Oscillator Control Register(1) Register 9-2: CLKDIV: Clock Divisor Register Register 9-3: PLLFBD: PLL Feedback Divisor Register Register 9-4: OSCTUN: FRC Oscillator Tuning Register Register 9-5: REFOCON: Reference Oscillator Control Register 10.0 Power-Saving Features 10.1 Clock Frequency and Clock Switching 10.2 Instruction-Based Power-Saving Modes EXAMPLE 10-1: PWRSAV Instruction Syntax 10.3 Doze Mode 10.4 Peripheral Module Disable 10.5 Power-Saving Resources Register 10-1: PMD1: Peripheral Module Disable Control Register 1 Register 10-2: PMD2: Peripheral Module Disable Control Register 2 Register 10-3: PMD3: Peripheral Module Disable Control Register 3 Register 10-4: PMD4: Peripheral Module Disable Control Register 4 Register 10-5: PMD6: Peripheral Module Disable control Register 6 Register 10-6: PMD7: Peripheral Module Disable control Register 7 11.0 I/O Ports 11.1 Parallel I/O (PIO) Ports FIGURE 11-1: Block Diagram of a Typical Shared Port Structure 11.2 Configuring Analog and Digital Port Pins 11.3 Input Change Notification (ICN) EXAMPLE 11-1: Port Write/Read Example 11.4 Peripheral Pin Select (PPS) FIGURE 11-2: Remappable Input for U1RX EXAMPLE 11-2: Connecting IC1 to the HOME1 QEI1 Digital Filter Input on Pin 43 of the dsPIC33EPXXXMC206 Device TABLE 11-1: Selectable Input Sources (Maps Input to Function) TABLE 11-2: Input Pin Selection for Selectable Input sources FIGURE 11-3: Multiplexing Remappable Output for RPn TABLE 11-3: Output Selection for Remappable Pins (RPn) 11.5 I/O Helpful Tips 11.6 I/O Ports Resources 11.7 Peripheral Pin Select Registers Register 11-1: RPINR0: Peripheral Pin Select Input Register 0 Register 11-2: RPINR1: Peripheral Pin Select Input Register 1 Register 11-3: RPINR3: Peripheral Pin Select Input Register 3 Register 11-4: RPINR7: Peripheral Pin Select Input Register 7 Register 11-5: RPINR8: Peripheral Pin Select Input Register 8 Register 11-6: RPINR11: Peripheral Pin Select Input Register 11 Register 11-7: RPINR12: Peripheral Pin Select Input Register 12 (dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X Devices Only) Register 11-8: RPINR14: Peripheral Pin Select Input Register 14 (dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X Devices Only) Register 11-9: RPINR15: Peripheral Pin Select Input Register 15 (dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X Devices Only) Register 11-10: RPINR18: Peripheral Pin Select Input Register 18 Register 11-11: RPINR19: Peripheral Pin Select Input Register 19 Register 11-12: RPINR22: Peripheral Pin Select Input Register 22 Register 11-13: RPINR23: Peripheral Pin Select Input Register 23 Register 11-14: RPINR26: Peripheral Pin Select Input Register 26 (dsPIC33EPXXXGP/MC50X Devices Only) Register 11-15: RPINR37: Peripheral Pin Select Input Register 37 (dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X Devices Only) Register 11-16: RPINR38: Peripheral Pin Select Input Register 38 (dsPIC33EPXXXMC20X and PIC24EPXXXMC20X Devices Only) Register 11-17: RPINR39: Peripheral Pin Select Input Register 39 (dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X Devices Only) Register 11-18: RPOR0: Peripheral Pin Select Output Register 0 Register 11-19: RPOR1: Peripheral Pin Select Output Register 1 Register 11-20: RPOR2: Peripheral Pin Select Output Register 2 Register 11-21: RPOR3: Peripheral Pin Select Output Register 3 Register 11-22: RPOR4: Peripheral Pin Select Output Register 4 Register 11-23: RPOR5: Peripheral Pin Select Output Register 5 Register 11-24: RPOR6: Peripheral Pin Select Output Register 6 Register 11-25: RPOR7: Peripheral Pin Select Output Register 7 Register 11-26: RPOR8: Peripheral Pin Select Output Register 8 Register 11-27: RPOR9: Peripheral Pin Select Output Register 9 12.0 Timer1 TABLE 12-1: Timer Mode Settings FIGURE 12-1: 16-bit Timer1 Module Block Diagram 12.1 Timer1 Resources 12.2 Timer1 Control Register Register 12-1: T1CON: Timer1 Control Register 13.0 Timer2/3 and Timer4/5 FIGURE 13-1: Type B Timer block Diagram (x = 2 and 4) FIGURE 13-2: Type C Timer Block Diagram (x = 3 and 5) FIGURE 13-3: Type B/Type C Timer Pair Block Diagram (32-Bit Timer) 13.1 Timerx/y Resources 13.2 Timer Control Registers Register 13-1: TxCON: (TIMER2 and Timer4) Control Register Register 13-2: TyCON: (TIMER3 and TIMER5) Control Register 14.0 Input Capture FIGURE 14-1: Input Capture x Module Block Diagram 14.1 Input Capture Resources 14.2 Input Capture Registers Register 14-1: ICxCON1: Input Capture X Control Register 1 Register 14-2: ICxCON2: Input Capture X Control Register 2 15.0 Output Compare FIGURE 15-1: Output Compare x Module Block Diagram 15.1 Output Compare Resources 15.2 Output Compare Control Registers Register 15-1: OCxCON1: Output Compare x Control Register 1 Register 15-2: OCxCON2: Output Compare x Control Register 2 16.0 High-Speed PWM Module (dsPIC33EPXXXMC20X/50X AND PIC24EPXXXMC20X Devices Only) 16.1 PWM Faults EXAMPLE 16-1: PWMx Write-Protected Register Unlock Sequence FIGURE 16-1: High-Speed PWMx Module Architectural Overview FIGURE 16-2: High-Speed PWMx Module Register Interconnection Diagram 16.2 PWM Resources 16.3 PWMx Control Registers Register 16-1: PTCON: PWMx Time Base Control Register Register 16-2: PTCON2: PWMx Primary Master Clock Divider Select Register 2 Register 16-3: PTPER: PWMx Primary Master Time Base Period Register Register 16-4: SEVTCMP: PWMx Primary Special Event Compare Register Register 16-5: CHOP: PWMx Chop Clock Generator Register Register 16-6: MDC: PWMx Master Duty Cycle Register Register 16-7: PWMCONx: PWMx Control Register Register 16-8: PDCx: PWMx Generator Duty Cycle Register Register 16-9: PHASEx: PWMx Primary Phase-Shift Register Register 16-10: DTRx: PWMx Dead-Time Register Register 16-11: ALTDTRx: PWMx Alternate Dead-Time Register Register 16-12: TRGCONx: PWMx Trigger Control Register Register 16-13: IOCONx: PWMx I/O Control Register(2) Register 16-14: TRIGx: PWMx Primary Trigger Compare Value Register Register 16-15: FCLCONx: PWMx Fault Current-Limit Control Register(1) Register 16-16: LEBCONx: PWMx Leading-Edge Blanking Control Register Register 16-17: LEBDLYx: PWMx Leading-Edge Blanking Delay Register Register 16-18: AUXCONx: PWMx Auxiliary Control Register 17.0 Quadrature Encoder Interface (QEI) Module (dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X Devices Only) FIGURE 17-1: QEI Block Diagram 17.1 QEI Resources 17.2 QEI Control Registers Register 17-1: QEI1CON: QEI1 Control Register Register 17-2: QEI1IOC: QEI1 I/O Control Register Register 17-3: QEI1STAT: QEI1 Status register Register 17-4: POS1CNTH: Position Counter 1 High Word Register Register 17-5: POS1CNTL: Position Counter 1 Low Word Register Register 17-6: POS1HLD: Position Counter 1 Hold Register Register 17-7: VEL1CNT: Velocity Counter 1 Register Register 17-8: INDX1CNTH: Index Counter 1 High Word Register Register 17-9: INDX1CNTL: Index Counter 1 Low Word Register Register 17-10: INDX1HLD: Index Counter 1 Hold Register Register 17-11: QEI1ICH: QEI1 Initialization/Capture High Word Register Register 17-12: QEI1ICL: QEI1 Initialization/Capture Low Word Register Register 17-13: QEI1LECH: qei1 Less Than or Equal Compare High Word Register Register 17-14: QEI1LECL: qei1 Less Than or Equal Compare Low Word Register Register 17-15: QEI1GECH: QEI1 Greater Than or Equal Compare High Word Register Register 17-16: QEI1GECL: QEI1 Greater Than or Equal Compare Low Word Register Register 17-17: INT1TMRH: Interval 1 Timer High Word Register Register 17-18: INT1TMRL: Interval 1 Timer Low Word Register Register 17-19: INT1HLDH: Interval 1 Timer Hold High Word Register Register 17-20: INT1HLDL: Interval 1 Timer Hold Low Word Register 18.0 Serial Peripheral Interface (SPI) FIGURE 18-1: SPIx Module Block Diagram 18.1 SPI Helpful Tips 18.2 SPI Resources 18.3 SPIx Control Registers Register 18-1: SPIxSTAT: SPIx Status and Control Register Register 18-2: SPIxCON1: SPIx Control Register 1 Register 18-3: SPIxCON2: SPIx Control Register 2 19.0 Inter-Integrated Circuit™ (I2C™) FIGURE 19-1: I2Cx Block Diagram (x = 1 or 2) 19.1 I2C Resources 19.2 I2C Control Registers Register 19-1: I2CxCON: I2Cx Control Register Register 19-2: I2CxSTAT: I2Cx Status Register Register 19-3: I2CxMSK: I2Cx Slave Mode Address Mask Register 20.0 Universal Asynchronous Receiver Transmitter (UART) FIGURE 20-1: UARTx Simplified Block Diagram 20.1 UART Helpful Tips 20.2 UART Resources 20.3 UARTx Control Registers Register 20-1: UxMODE: UARTx Mode Register Register 20-2: UxSTA: UARTx Status and Control Register 21.0 Enhanced CAN (ECAN™) Module (dsPIC33EPXXXGP/ MC50X Devices Only) 21.1 Overview FIGURE 21-1: ECAN™ Module Block Diagram 21.2 Modes of Operation 21.3 ECAN Resources 21.4 ECAN Control Registers Register 21-1: CxCTRL1: ECANx CONTROL REGISTER 1 Register 21-2: CxCTRL2: ECANx Control Register 2 Register 21-3: CxVEC: ECANx Interrupt Code Register Register 21-4: CxFCTRL: ECANx FIFO Control Register Register 21-5: CxFIFO: ECANx FIFO Status Register Register 21-6: CxINTF: ECANx Interrupt Flag Register Register 21-7: CxINTE: ECANx Interrupt Enable Register Register 21-8: CxEC: ECANx Transmit/Receive Error Count Register Register 21-9: CxCFG1: ECANx Baud Rate Configuration Register 1 Register 21-10: CxCFG2: ECANx Baud Rate Configuration Register 2 Register 21-11: CxFEN1: ECANx Acceptance Filter Enable Register 1 Register 21-12: CxBUFPNT1: ECANx Filter 0-3 Buffer Pointer Register 1 Register 21-13: CxBUFPNT2: ECANx Filter 4-7 Buffer Pointer Register 2 Register 21-14: CxBUFPNT3: ECANx Filter 8-11 Buffer Pointer Register 3 Register 21-15: CxBUFPNT4: ECANx Filter 12-15 Buffer Pointer Register 4 Register 21-16: CxRXFnSID: ECANx Acceptance Filter n Standard Identifier Register (n = 0-15) Register 21-17: CxRXFnEID: ECANx Acceptance Filter n Extended Identifier Register (n = 0-15) Register 21-18: CxFMSKSEL1: ECANx Filter 7-0 Mask Selection Register 1 Register 21-19: CxFMSKSEL2: ECANx Filter 15-8 Mask Selection Register 2 Register 21-20: CxRXMnSID: ECANx Acceptance Filter Mask n Standard Identifier Register (n = 0-2) Register 21-21: CxRXMnEID: ECANx Acceptance Filter Mask n Extended Identifier Register (n = 0-2) Register 21-22: CxRXFUL1: ECANx Receive Buffer Full Register 1 Register 21-23: CxRXFUL2: ECANx Receive Buffer Full Register 2 Register 21-24: CxRXOVF1: ECANx Receive Buffer Overflow Register 1 Register 21-25: CxRXOVF2: ECANx Receive Buffer Overflow Register 2 Register 21-26: CxTRmnCON: ECANx TX/RX Buffer mn Control Register (m = 0,2,4,6; n = 1,3,5,7) 21.5 ECAN Message Buffers 22.0 Charge Time Measurement Unit (CTMU) FIGURE 22-1: CTMU Block Diagram 22.1 CTMU Resources 22.2 CTMU Control Registers Register 22-1: CTMUCON1: CTMU Control Register 1 Register 22-2: CTMUCON2: CTMU Control Register 2 Register 22-3: CTMUICON: CTMU Current Control Register 23.0 10-Bit/12-Bit Analog-to-Digital Converter (ADC) 23.1 Key Features FIGURE 23-1: ADC Module Block Diagram with Connection Options for ANx pins and Op Amps FIGURE 23-2: ADC Conversion Clock Period Block Diagram 23.2 ADC Helpful Tips 23.3 ADC Resources 23.4 ADC Control Registers Register 23-1: AD1CON1: ADC1 Control Register 1 Register 23-2: AD1CON2: ADC1 Control Register 2 Register 23-3: AD1CON3: ADC1 Control Register 3 Register 23-4: AD1CON4: ADC1 Control Register 4 Register 23-5: AD1CHS123: ADC1 Input Channel 1, 2, 3 Select Register Register 23-6: AD1CHS0: ADC1 Input Channel 0 Select Register Register 23-7: AD1CSSH: ADC1 Input Scan Select Register High(1) Register 23-8: AD1CSSL: ADC1 Input Scan Select Register Low(1,2) 24.0 Peripheral Trigger Generator (PTG) Module 24.1 Module Introduction FIGURE 24-1: PTG Block Diagram 24.2 PTG Resources 24.3 PTG Control Registers Register 24-1: PTGCST: PTG control/Status Register Register 24-2: PTGCON: PTG control Register Register 24-3: PTGBTE: PTG Broadcast Trigger Enable Register(1,2) Register 24-4: PTGT0LIM: PTG Timer0 Limit Register(1) Register 24-5: PTGT1LIM: PTG Timer1 Limit Register(1) Register 24-6: PTGSDLIM: PTG Step Delay Limit Register(1,2) Register 24-7: PTGC0LIM: PTG Counter 0 Limit Register(1) Register 24-8: PTGC1LIM: PTG Counter 1 Limit Register(1) Register 24-9: PTGHOLD: PTG Hold Register(1) Register 24-10: PTGADJ: PTG Adjust Register(1) Register 24-11: PTGL0: PTG Literal 0 Register(1) Register 24-12: PTGQPTR: PTG Step Queue Pointer Register(1) Register 24-13: PTGQUEx: PTG Step Queue Register x (x = 0-7)(1,3) 24.4 Step Commands and Format TABLE 24-1: PTG Step Command Format TABLE 24-1: PTG STEP Command Format (continued) TABLE 24-1: PTG STEP Command Format (continued) TABLE 24-2: PTG Output Descriptions 25.0 Op Amp/Comparator Module FIGURE 25-1: Op Amp/Comparator x Module Block Diagram (Modules 1, 2 and 3) FIGURE 25-2: Comparator Module Block Diagram (Module 4) FIGURE 25-3: Op Amp/Comparator Voltage Reference Block Diagram FIGURE 25-4: User-Programmable Blanking Function Block Diagram FIGURE 25-5: Digital Filter Interconnect Block Diagram 25.1 Op Amp Application Considerations FIGURE 25-6: Op Amp Configuration A 25.2 Op Amp/Comparator Resources FIGURE 25-7: Op Amp Configuration B 25.3 Op Amp/Comparator Registers Register 25-1: CMSTAT: Op Amp/Comparator Status Register Register 25-2: CMxCON: Comparator x Control Register (x = 1, 2 or 3) Register 25-3: CM4CON: Comparator 4 Control Register Register 25-4: CMxMSKSRC: Comparator x Mask Source Select Control Register Register 25-5: CMxMSKCON: Comparator x Mask Gating Control Register Register 25-6: CMxFLTR: Comparator x Filter Control Register Register 25-7: CVRCON: Comparator Voltage Reference Control Register 26.0 Programmable Cyclic Redundancy Check (CRC) Generator FIGURE 26-1: CRC Block Diagram FIGURE 26-2: CRC Shift Engine Detail 26.1 Overview TABLE 26-1: CRC SETUP Examples FOR 16 and 32-bit polynomial 26.2 Programmable CRC Resources 26.3 Programmable CRC Registers Register 26-1: CRCCON1: CRC Control Register 1 Register 26-2: CRCCON2: CRC Control Register 2 Register 26-3: CRCXORH: CRC XOR Polynomial HIGH Register Register 26-4: CRCXORL: CRC XOR Polynomial Low Register 27.0 Special Features 27.1 Configuration Bits TABLE 27-1: Configuration Byte Register Map TABLE 27-2: Configuration Bits Description Register 27-1: DEVID: Device ID Register Register 27-2: DEVREV: Device Revision Register 27.2 User ID Words TABLE 27-3: User ID Words Register Map 27.3 On-Chip Voltage Regulator FIGURE 27-1: Connections for the On-Chip Voltage Regulator(1,2,3) 27.4 Brown-out Reset (BOR) 27.5 Watchdog Timer (WDT) FIGURE 27-2: WDT Block diagram 27.6 JTAG Interface 27.7 In-Circuit Serial Programming 27.8 In-Circuit Debugger 27.9 Code Protection and CodeGuard™ Security 28.0 Instruction Set Summary TABLE 28-1: Symbols used in Opcode Descriptions TABLE 28-2: Instruction Set Overview 29.0 Development Support 29.1 MPLAB X Integrated Development Environment Software 29.2 MPLAB XC Compilers 29.3 MPASM Assembler 29.4 MPLINK Object Linker/ MPLIB Object Librarian 29.5 MPLAB Assembler, Linker and Librarian for Various Device Families 29.6 MPLAB X SIM Software Simulator 29.7 MPLAB REAL ICE In-Circuit Emulator System 29.8 MPLAB ICD 3 In-Circuit Debugger System 29.9 PICkit 3 In-Circuit Debugger/ Programmer 29.10 MPLAB PM3 Device Programmer 29.11 Demonstration/Development Boards, Evaluation Kits and Starter Kits 29.12 Third-Party Development Tools 30.0 Electrical Characteristics 30.1 DC Characteristics TABLE 30-1: Operating MIPS vs. Voltage TABLE 30-2: Thermal Operating Conditions TABLE 30-3: Thermal Packaging Characteristics TABLE 30-4: DC Temperature and Voltage specifications TABLE 30-5: Filter Capacitor (Cefc) Specifications TABLE 30-6: DC Characteristics: Operating Current (Idd) TABLE 30-7: DC Characteristics: Idle Current (iidle) TABLE 30-8: DC Characteristics: Power-Down Current (Ipd) TABLE 30-9: DC Characteristics: Watchdog Timer Delta Current (DIwdt)(1) TABLE 30-10: DC Characteristics: doze Current (Idoze) TABLE 30-11: DC Characteristics: I/O Pin Input Specifications TABLE 30-12: DC Characteristics: I/O Pin Output Specifications TABLE 30-13: Electrical Characteristics: BOR TABLE 30-14: DC Characteristics: Program Memory 30.2 AC Characteristics and Timing Parameters TABLE 30-15: Temperature and Voltage Specifications – AC FIGURE 30-1: Load Conditions for Device Timing Specifications TABLE 30-16: Capacitive Loading Requirements on Output Pins FIGURE 30-2: External Clock Timing TABLE 30-17: External Clock Timing Requirements TABLE 30-18: PLL Clock Timing Specifications TABLE 30-19: Internal FRC Accuracy TABLE 30-20: Internal LPRC accuracy FIGURE 30-3: I/O Timing Characteristics TABLE 30-21: I/O Timing Requirements FIGURE 30-4: BOR and Master Clear Reset Timing Characteristics TABLE 30-22: Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer Timing Requirements FIGURE 30-5: Timer1-Timer5 External Clock Timing Characteristics TABLE 30-23: Timer1 External Clock Timing Requirements(1) TABLE 30-24: Timer2 and Timer4 (Type B Timer) External Clock Timing Requirements TABLE 30-25: Timer3 and Timer5 (Type C Timer) External Clock Timing Requirements FIGURE 30-6: INPUT CAPTURE x (ICx) TIMING Characteristics Table 30-26: Input Capture x Module Timing Requirements FIGURE 30-7: Output Compare x Module (OCx) Timing Characteristics TABLE 30-27: Output Compare x Module timing requirements FIGURE 30-8: OCx/PWMx Module Timing Characteristics TABLE 30-28: OCx/PWMx MODE Timing Requirements FIGURE 30-9: High-Speed PWMx Module Fault Timing Characteristics (dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X Devices Only) FIGURE 30-10: High-Speed PWMx Module Timing Characteristics (dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X Devices Only) TABLE 30-29: High-Speed PWMx Module Timing Requirements (dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X Devices Only) FIGURE 30-11: TimerQ (QEI Module) External Clock Timing Characteristics (dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X Devices Only) TABLE 30-30: QEI module External Clock Timing Requirements (dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X Devices Only) FIGURE 30-12: QEA/QEB Input Characteristics (dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X Devices Only) TABLE 30-31: Quadrature Decoder Timing Requirements (dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X Devices Only) FIGURE 30-13: QEI Module Index Pulse Timing Characteristics (dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X Devices Only) TABLE 30-32: QEI INDEX PULSE Timing Requirements (dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X Devices Only) TABLE 30-33: SPI2 Maximum Data/Clock Rate Summary FIGURE 30-14: SPI2 MASTER MODE (Half-Duplex, Transmit Only, CKE = 0) TIMING CHARACTERISTICS FIGURE 30-15: SPI2 MASTER MODE (Half-Duplex, Transmit Only, CKE = 1) TIMING CHARACTERISTICS TABLE 30-34: SPI2 Master Mode (Half-Duplex, Transmit Only) Timing Requirements FIGURE 30-16: SPI2 MASTER MODE (Full-Duplex, CKE = 1, CKP = x, SMP = 1) TIMING CHARACTERISTICS TABLE 30-35: SPI2 Master Mode (Full-Duplex, CKE = 1, CKP = x, SMP = 1) Timing Requirements FIGURE 30-17: SPI2 MASTER MODE (Full-Duplex, CKE = 0, CKP = x, SMP = 1) TIMING CHARACTERISTICS TABLE 30-36: SPI2 Master Mode (Full-Duplex, CKE = 0, CKP = x, SMP = 1) Timing Requirements FIGURE 30-18: SPI2 SLAVE MODE (Full-Duplex, CKE = 1, CKP = 0, SMP = 0) TIMING CHARACTERISTICS TABLE 30-37: SPI2 Slave Mode (Full-Duplex, CKE = 1, CKP = 0, SMP = 0) Timing Requirements FIGURE 30-19: SPI2 SLAVE MODE (Full-Duplex, CKE = 1, CKP = 1, SMP = 0) TIMING CHARACTERISTICS TABLE 30-38: SPI2 Slave Mode (Full-Duplex, CKE = 1, CKP = 1, SMP = 0) Timing Requirements FIGURE 30-20: SPI2 SLAVE MODE (Full-Duplex, CKE = 0, CKP = 1, SMP = 0) TIMING CHARACTERISTICS TABLE 30-39: SPI2 Slave Mode (Full-Duplex, CKE = 0, CKP = 1, SMP = 0) Timing Requirements FIGURE 30-21: SPI2 SLAVE MODE (Full-Duplex, CKE = 0, CKP = 0, SMP = 0) TIMING CHARACTERISTICS TABLE 30-40: SPI2 Slave Mode (Full-Duplex, CKE = 0, CKP = 0, SMP = 0) Timing Requirements TABLE 30-41: SPI1 Maximum Data/Clock Rate Summary FIGURE 30-22: SPI1 MASTER MODE (Half-Duplex, Transmit Only, CKE = 0) TIMING CHARACTERISTICS FIGURE 30-23: SPI1 MASTER MODE (Half-Duplex, Transmit Only, CKE = 1) TIMING CHARACTERISTICS TABLE 30-42: SPI1 Master Mode (Half-Duplex, Transmit Only) Timing Requirements FIGURE 30-24: SPI1 MASTER MODE (Full-Duplex, CKE = 1, CKP = x, SMP = 1) TIMING CHARACTERISTICS TABLE 30-43: SPI1 Master Mode (Full-Duplex, CKE = 1, CKP = x, SMP = 1) Timing Requirements FIGURE 30-25: SPI1 MASTER MODE (Full-Duplex, CKE = 0, CKP = x, SMP = 1) TIMING CHARACTERISTICS TABLE 30-44: SPI1 Master Mode (Full-Duplex, CKE = 0, CKP = x, SMP = 1) Timing Requirements FIGURE 30-26: SPI1 SLAVE MODE (Full-Duplex, CKE = 1, CKP = 0, SMP = 0) TIMING CHARACTERISTICS TABLE 30-45: SPI1 Slave Mode (Full-Duplex, CKE = 1, CKP = 0, SMP = 0) Timing Requirements FIGURE 30-27: SPI1 SLAVE MODE (Full-Duplex, CKE = 1, CKP = 1, SMP = 0) TIMING CHARACTERISTICS TABLE 30-46: SPI1 Slave Mode (Full-Duplex, CKE = 1, CKP = 1, SMP = 0) Timing Requirements FIGURE 30-28: SPI1 SLAVE MODE (Full-Duplex, CKE = 0, CKP = 1, SMP = 0) TIMING CHARACTERISTICS TABLE 30-47: SPI1 Slave Mode (Full-Duplex, CKE = 0, CKP = 1, SMP = 0) Timing Requirements FIGURE 30-29: SPI1 SLAVE MODE (Full-Duplex, CKE = 0, CKP = 0, SMP = 0) TIMING CHARACTERISTICS TABLE 30-48: SPI1 Slave Mode (Full-Duplex, CKE = 0, CKP = 0, SMP = 0) Timing Requirements FIGURE 30-30: I2Cx Bus Start/Stop Bits Timing Characteristics (Master Mode) FIGURE 30-31: I2Cx Bus Data Timing Characteristics (Master mode) TABLE 30-49: I2Cx Bus Data Timing Requirements (Master Mode) FIGURE 30-32: I2Cx Bus Start/Stop Bits Timing Characteristics (slave mode) FIGURE 30-33: I2Cx Bus Data Timing Characteristics (slave mode) TABLE 30-50: I2Cx Bus Data Timing Requirements (Slave Mode) FIGURE 30-34: ECANx Module I/O Timing Characteristics TABLE 30-51: ECANx Module I/O Timing Requirements FIGURE 30-35: UARTx Module I/O Timing Characteristics TABLE 30-52: UARTx Module I/O Timing Requirements TABLE 30-53: Op Amp/Comparator Specifications TABLE 30-54: Op Amp/Comparator Voltage Reference Settling Time Specifications TABLE 30-55: Op Amp/Comparator Voltage Reference Specifications TABLE 30-56: CTMU Current Source Specifications TABLE 30-57: ADC Module Specifications TABLE 30-58: ADC Module Specifications (12-bit Mode) TABLE 30-59: ADC Module Specifications (10-bit Mode) FIGURE 30-36: ADC Conversion (12-bit mode) Timing Characteristics (asam = 0, ssrc<2:0> = 000, SSRCG = 0) TABLE 30-60: ADC Conversion (12-bit Mode) Timing Requirements FIGURE 30-37: ADC Conversion (10-bit mode) Timing Characteristics (chps<1:0> = 01, SIMSAM = 0, asam = 0, ssrc<2:0> = 000, SSRCG = 0) FIGURE 30-38: ADC Conversion (10-bit mode) Timing Characteristics (chps<1:0> = 01, SIMSAM = 0, asam = 1, ssrc<2:0> = 111, SSRCG = 0, SAMC<4:0> = 00010) TABLE 30-61: ADC CONVERSION (10-bit mode) TIMING Requirements TABLE 30-62: DMA Module Timing Requirements 31.0 High-Temperature Electrical Characteristics 31.1 High-Temperature DC Characteristics TABLE 31-1: Operating MIPS vs. Voltage TABLE 31-2: Thermal Operating Conditions TABLE 31-3: DC Temperature and Voltage Specifications TABLE 31-4: DC Characteristics: Power-down Current (Ipd) TABLE 31-5: DC Characteristics: IDLE CURRENT (Iidle) TABLE 31-6: DC Characteristics: Operating Current (Idd) TABLE 31-7: DC Characteristics: Doze Current (Idoze) TABLE 31-8: DC Characteristics: I/O Pin Output Specifications 31.2 AC Characteristics and Timing Parameters TABLE 31-9: Temperature and Voltage Specifications – AC FIGURE 31-1: Load Conditions for Device Timing Specifications TABLE 31-10: PLL Clock Timing Specifications TABLE 31-11: Internal RC accuracy TABLE 31-12: ADC Module Specifications (12-bit Mode) TABLE 31-13: ADC Module Specifications (10-bit Mode) 32.0 DC and AC Device Characteristics Graphs FIGURE 32-1: Voh – 4x Driver Pins FIGURE 32-2: Voh – 8x Driver Pins FIGURE 32-3: Vol – 4x Driver Pins FIGURE 32-4: Vol – 8x Driver Pins FIGURE 32-5: Typical Ipd Current @ Vdd = 3.3V FIGURE 32-6: Typical/Maximum Idd Current @ Vdd = 3.3V FIGURE 32-7: Typical Idoze Current @ Vdd = 3.3V FIGURE 32-8: Typical Iidle Current @ Vdd = 3.3V FIGURE 32-9: Typical FRC Frequency @ Vdd = 3.3V FIGURE 32-10: Typical LPRC Frequency @ Vdd = 3.3V FIGURE 32-11: Typical CTMU Temperature DIODE Forward Voltage 33.0 Packaging Information 33.1 Package Marking Information 33.1 Package Marking Information (Continued) 33.1 Package Marking Information (Continued) 33.2 Package Details Appendix A: Revision History TABLE A-1: Major Section Updates TABLE A-2: Major Section Updates TABLE A-3: Major Section Updates TABLE A-4: Major Section Updates TABLE A-5: Major Section Updates TABLE A-6: Major Section Updates INDEX The Microchip Web Site Customer Change Notification Service Customer Support