Datasheet PIC16F1788, PIC16F1789 (Microchip) - 4

link to page 9 link to page 9
PIC16(L)F1788/9 Pin Diagram – 28-Pin SPDIP, SOIC, SSOP
VPP/MCLR/RE3 1 28 RB7/ICSPDAT RA0 2 27 RB6/ICSPCLK RA1 3 26 RB5 RA2 4 25 RB4 RA3 5
8
24 RB3 RA4 6
78
23 RB2
1
RA5 7 22 RB1 VSS 8
6(L)F
21 RB0
1
RA7 9
C
20 VDD
PI
10 19 VSS RA6 11 18 RC0 RC7 12 17 RC1 RC6 RC2 13 16 RC5 RC3 14 15 RC4
Note:
See Table 1 for the location of all peripheral functions.
Pin Diagram – 28-Pin QFN QFN
PP T /V A LK D C LR P P C S S /IC /IC 3/M E RA1 RA0 R RB7 RB6 RB5 RB4 28 27 26 25 24 23 22 RA2 1 21 RB3 RA3 2 20 RB2 RA4 3 19 RB1 RA5 4
PIC16(L)F1788
18 RB0 VSS 5 17 VDD RA7 6 16 VSS RA6 7 15 RC7 8 9 10 11 12 13 14 RC0 RC1 RC2 RC3 RC4 RC5 RC6
Note:
See Table 1 for the location of all peripheral functions. DS40001675C-page 4  2013-2015 Microchip Technology Inc. Document Outline High-Performance RISC CPU: Memory Features: High-Performance PWM Controller: Extreme Low-Power Management PIC16LF1788/9 with XLP: Analog Peripheral Features: I/O Features: Digital Peripheral Features: Oscillator Features: General Microcontroller Features: PIC16(L)F178X Family Types Pin Diagram – 28-Pin SPDIP, SOIC, SSOP Pin Diagram – 28-Pin QFN Pin Diagram – 40-Pin PDIP Pin Diagram – 40-Pin UQFN (5x5) Pin Diagram – 44-Pin QFN Pin Diagram – 44-Pin TQFP TABLE 1: 28-Pin Allocation Table (PIC16(L)F1788) TABLE 2: 40/44-Pin Allocation Table (PIC16(L)F1789) Table of Contents 1.0 Device Overview TABLE 1-1: Device Peripheral Summary FIGURE 1-1: PIC16(L)F1788/9 Block Diagram TABLE 1-2: PIC16(L)F1788 Pinout Description TABLE 1-3: PIC16(L)F1789 Pinout Description 2.0 Enhanced Mid-Range CPU FIGURE 2-1: Core Block Diagram 2.1 Automatic Interrupt Context Saving 2.2 16-Level Stack with Overflow and Underflow 2.3 File Select Registers 2.4 Instruction Set 3.0 Memory Organization 3.1 Program Memory Organization TABLE 3-1: Device Sizes and Addresses FIGURE 3-1: Program Memory Map and Stack for PIC16(L)F1788/9 3.1.1 Reading Program Memory as Data EXAMPLE 3-1: RETLW Instruction EXAMPLE 3-2: Accessing Program Memory Via FSR 3.2 Data Memory Organization 3.2.1 Core Registers TABLE 3-2: Core Registers 3.3 Register Definitions: Status Register 3-1: STATUS: STATUS Register 3.3.1 Special Function Register 3.3.2 General Purpose RAM 3.3.3 Common RAM FIGURE 3-2: Banked Memory Partitioning 3.3.4 Device Memory Maps TABLE 3-3: PIC16(L)F1788 Memory Map (Banks 0-7) TABLE 3-4: PIC16(L)F1789 Memory Map (Banks 0-7) TABLE 3-5: PIC16(L)F1788/9 Memory Map (Banks 8-28) TABLE 3-6: PIC16(L)F1788/9 Memory Map (Bank 10 Details) TABLE 3-7: PIC16(L)F1788/9 Memory Map (Bank 11 Details) TABLE 3-8: PIC16(L)F1788/9 Memory Map (Bank 31 Details) TABLE 3-9: PIC16(L)F1788/9 Memory Map (Bank 29 Details) TABLE 3-10: PIC16(L)F1788/9 Memory Map (Bank 30 Details) 3.3.5 Core Function Registers Summary TABLE 3-11: Core Function Registers Summary TABLE 3-12: Special Function Register Summary 3.4 PCL and PCLATH FIGURE 3-3: Loading of PC in Different Situations 3.4.1 Modifying PCL 3.4.2 Computed GOTO 3.4.3 Computed Function Calls 3.4.4 Branching 3.5 Stack 3.5.1 Accessing the Stack FIGURE 3-4: Accessing the Stack Example 1 FIGURE 3-5: Accessing the Stack Example 2 FIGURE 3-6: Accessing the Stack Example 3 FIGURE 3-7: Accessing the Stack Example 4 3.5.2 Overflow/Underflow Reset 3.6 Indirect Addressing FIGURE 3-8: Indirect Addressing 3.6.1 Traditional Data Memory FIGURE 3-9: Traditional Data Memory Map 3.6.2 Linear Data Memory FIGURE 3-10: Linear Data Memory Map 3.6.3 Program Flash Memory FIGURE 3-11: Program Flash Memory Map 4.0 Device Configuration 4.1 Configuration Words 4.2 Register Definitions: Configuration Words Register 4-1: CONFIG1: Configuration Word 1 Register 4-2: CONFIG2: Configuration Word 2 4.3 Code Protection 4.3.1 Program Memory Protection 4.3.2 Data EEPROM Protection 4.4 Write Protection 4.5 User ID 4.6 Device ID and Revision ID 4.7 Register Definitions: Device and Revision Register 4-3: DevID: Device ID Register Register 4-4: RevID: Revision ID Register 5.0 Resets FIGURE 5-1: Simplified Block Diagram of On-Chip Reset Circuit 5.1 Power-On Reset (POR) 5.1.1 Power-up Timer (PWRT) 5.2 Brown-Out Reset (BOR) TABLE 5-1: BOR Operating Modes 5.2.1 BOR is Always On 5.2.2 BOR is Off in Sleep 5.2.3 BOR Controlled by Software FIGURE 5-2: Brown-Out Situations 5.3 Register Definitions: BOR Control Register 5-1: BORCON: Brown-Out Reset Control Register 5.4 Low-Power Brown-Out Reset (LPBOR) 5.4.1 Enabling LPBOR 5.5 MCLR TABLE 5-2: MCLR Configuration 5.5.1 MCLR Enabled 5.5.2 MCLR Disabled 5.6 Watchdog Timer (WDT) Reset 5.7 RESET Instruction 5.8 Stack Overflow/Underflow Reset 5.9 Programming Mode Exit 5.10 Power-Up Timer 5.11 Start-up Sequence FIGURE 5-3: Reset Start-up Sequence 5.12 Determining the Cause of a Reset TABLE 5-3: Reset Status Bits and Their Significance TABLE 5-4: Reset Condition for Special Registers 5.13 Power Control (PCON) Register 5.14 Register Definitions: Power Control Register 5-2: PCON: Power Control Register TABLE 5-5: Summary of Registers Associated with Resets 6.0 Oscillator Module (with Fail-Safe Clock Monitor) 6.1 Overview FIGURE 6-1: Simplified PIC® MCU Clock Source Block Diagram 6.2 Clock Source Types 6.2.1 External Clock Sources FIGURE 6-2: External Clock (EC) Mode Operation FIGURE 6-3: Quartz Crystal Operation (LP, XT or HS Mode) FIGURE 6-4: Ceramic Resonator Operation (XT or HS Mode) FIGURE 6-5: Quartz Crystal Operation (Timer1 Oscillator) FIGURE 6-6: External RC Modes 6.2.2 Internal Clock Sources FIGURE 6-7: Internal Oscillator Switch Timing 6.3 Clock Switching 6.3.1 System Clock Select (SCS) Bits 6.3.2 Oscillator Start-up Timer Status (OSTS) Bit 6.3.3 Timer1 Oscillator 6.3.4 Timer1 Oscillator Ready (T1OSCR) Bit 6.3.5 Clock Switching Before Sleep 6.4 Two-Speed Clock Start-up Mode 6.4.1 Two-Speed Start-up Mode Configuration TABLE 6-1: Oscillator Switching Delays 6.4.2 Two-speed Start-up Sequence 6.4.3 Checking Two-Speed Clock Status FIGURE 6-8: Two-Speed Start-up 6.5 Fail-Safe Clock Monitor FIGURE 6-9: FSCM Block Diagram 6.5.1 Fail-Safe Detection 6.5.2 Fail-Safe Operation 6.5.3 Fail-Safe Condition Clearing 6.5.4 Reset or Wake-up from Sleep FIGURE 6-10: FSCM Timing Diagram 6.6 Register Definitions: Oscillator Control Register 6-1: OSCCON: Oscillator Control Register Register 6-2: OSCSTAT: Oscillator Status Register Register 6-3: OSCTUNE: Oscillator Tuning Register TABLE 6-2: Summary of Registers Associated with Clock Sources TABLE 6-3: Summary of Configuration Word with Clock Sources 7.0 Reference Clock Module 7.1 Slew Rate 7.2 Effects of a Reset 7.3 Operation During Sleep 7.4 Register Definition: Reference Clock Control Register 7-1: CLKRCON: Reference Clock Control Register TABLE 7-1: Summary of Registers Associated with Reference Clock Sources TABLE 7-2: Summary of Configuration Word with Reference Clock Sources 8.0 Interrupts FIGURE 8-1: Interrupt Logic 8.1 Operation 8.2 Interrupt Latency FIGURE 8-2: Interrupt Latency FIGURE 8-3: INT Pin Interrupt Timing 8.3 Interrupts During Sleep 8.4 INT Pin 8.5 Automatic Context Saving 8.6 Register Definitions: Interrupt Control Register 8-1: INTCON: Interrupt Control Register Register 8-2: PIE1: Peripheral Interrupt Enable Register 1 Register 8-3: PIE2: Peripheral Interrupt Enable Register 2 Register 8-4: PIE3: Peripheral Interrupt Enable Register 3 Register 8-5: PIE4: Peripheral Interrupt Enable Register 4 Register 8-6: PIR1: Peripheral Interrupt Request Register 1 Register 8-7: PIR2: Peripheral Interrupt Request Register 2 Register 8-8: PIR3: Peripheral Interrupt Request Register 3 Register 8-9: PIR4: Peripheral Interrupt Request Register 4 TABLE 8-1: Summary of Registers Associated with Interrupts 9.0 Power-Down Mode (Sleep) 9.1 Wake-up from Sleep 9.1.1 Wake-up Using Interrupts FIGURE 9-1: Wake-Up From Sleep Through Interrupt 9.2 Low-Power Sleep Mode 9.2.1 Sleep Current vs. Wake-up Time 9.2.2 Peripheral Usage in Sleep 9.3 Register Definitions: Voltage Regulator Control Register 9-1: VREGCON: Voltage Regulator Control Register(1) TABLE 9-1: Summary of Registers Associated with Power-Down Mode 10.0 Low Dropout (LDO) Voltage Regulator TABLE 10-1: VCAPEN Select Bit TABLE 10-2: Summary of Configuration Word with LDO 11.0 Watchdog Timer (WDT) FIGURE 11-1: Watchdog Timer Block Diagram 11.1 Independent Clock Source 11.2 WDT Operating Modes 11.2.1 WDT is Always On 11.2.2 WDT is Off in Sleep 11.2.3 WDT Controlled By Software TABLE 11-1: WDT Operating Modes 11.3 Time-Out Period 11.4 Clearing the WDT 11.5 Operation During Sleep TABLE 11-2: WDT Clearing Conditions 11.6 Register Definitions: Watchdog Control Register 11-1: WDTCON: Watchdog Timer Control Register TABLE 11-3: Summary of Registers Associated with Watchdog Timer TABLE 11-4: Summary of Configuration Word with Watchdog Timer 12.0 Data EEPROM and Flash Program Memory Control 12.1 EEADRL and EEADRH Registers 12.1.1 EECON1 and EECON2 Registers 12.2 Using the Data EEPROM 12.2.1 Reading the Data EEPROM Memory EXAMPLE 12-1: Data EEPROM Read 12.2.2 Writing to the Data EEPROM Memory 12.2.3 Protection Against Spurious Write 12.2.4 Data EEPROM Operation During Code-Protect EXAMPLE 12-2: Data EEPROM Write FIGURE 12-1: Flash Program Memory Read Cycle Execution 12.3 Flash Program Memory Overview 12.3.1 Reading the Flash Program Memory TABLE 12-1: Flash Memory Organization by Device EXAMPLE 12-3: Flash Program Memory Read 12.3.2 Erasing Flash Program Memory 12.3.3 Writing to Flash Program Memory FIGURE 12-2: Block Writes to Flash Program Memory With 32 Write Latches EXAMPLE 12-4: Erasing One Row of Program Memory EXAMPLE 12-5: Writing to Flash Program Memory EXAMPLE 12-6: Writing to Flash Program Memory 12.4 Modifying Flash Program Memory 12.5 User ID, Device ID and Configuration Word Access TABLE 12-2: User ID, Device ID and Configuration Word Access (CFGS = 1) EXAMPLE 12-7: Configuration Word and Device ID Access 12.6 Write Verify EXAMPLE 12-8: EEPROM Write Verify 12.7 Register Definitions: EEPROM and Flash Control Register 12-1: EEDATL: EEPROM Data Low Byte Register Register 12-2: EEDATH: EEPROM Data High Byte Register Register 12-3: EEADRL: EEPROM Address Register Register 12-4: EEADRH: EEPROM Address High Byte Register Register 12-5: EECON1: EEPROM Control 1 Register Register 12-6: EECON2: EEPROM Control 2 Register TABLE 12-3: Summary of Registers Associated with Data EEPROM 13.0 I/O Ports TABLE 13-1: Port Availability Per Device FIGURE 13-1: Generic I/O Port Operation 13.1 Alternate Pin Function 13.2 Register Definitions: Alternate Pin Function Control Register 13-1: APFCON1: Alternate Pin Function Control 1 Register Register 13-2: APFCON2: Alternate Pin Function Control 2 Register 13.3 PORTA Registers 13.3.1 Data Register 13.3.2 Direction Control 13.3.3 Open-Drain Control 13.3.4 Slew Rate Control 13.3.5 Input Threshold Control 13.3.6 Analog Control EXAMPLE 13-1: Initializing PORTA 13.3.7 PORTA Functions and Output Priorities TABLE 13-2: PORTA Output Priority 13.4 Register Definitions: PORTA Register 13-3: PORTA: PORTA Register Register 13-4: TRISA: PORTA Tri-State Register Register 13-5: LATA: PORTA Data Latch Register Register 13-6: ANSELA: PORTA Analog Select Register Register 13-7: WPUA: Weak Pull-Up PORTA Register Register 13-8: ODCONA: PORTA Open-Drain Control Register Register 13-9: SLRCONA: PORTA Slew Rate Control Register Register 13-10: INLVLA: PORTA Input Level Control Register TABLE 13-3: Summary of Registers Associated with PORTA TABLE 13-4: Summary of Configuration Word with PORTA 13.5 PORTB Registers 13.5.1 Data Register 13.5.2 Direction Control 13.5.3 Open-Drain Control 13.5.4 Slew Rate Control 13.5.5 Input Threshold Control 13.5.6 Analog Control 13.5.7 PORTB Functions and Output Priorities TABLE 13-5: PORTB Output Priority 13.6 Register Definitions: PORTB Register 13-11: PORTB: PORTB Register Register 13-12: TRISB: PORTB Tri-State Register Register 13-13: LATB: PORTB Data Latch Register Register 13-14: ANSELB: PORTB Analog Select Register Register 13-15: WPUB: Weak Pull-Up PORTB Register Register 13-16: ODCONB: PORTB Open-Drain Control Register Register 13-17: SLRCONB: PORTB Slew Rate Control Register Register 13-18: INLVLB: PORTB Input Level Control Register TABLE 13-6: Summary of Registers Associated with PORTB 13.7 PORTC Registers 13.7.1 Data Register 13.7.2 Direction Control 13.7.3 Open-Drain Control 13.7.4 Slew Rate Control 13.7.5 Input Threshold Control 13.7.6 PORTC Functions and Output Priorities TABLE 13-7: PORTC Output Priority 13.8 Register Definitions: PORTC Register 13-19: PORTC: PORTC Register Register 13-20: TRISC: PORTC Tri-State Register Register 13-21: LATC: PORTC Data Latch Register Register 13-22: WPUC: Weak Pull-Up PORTC Register Register 13-23: ODCONC: PORTC Open-Drain Control Register Register 13-24: SLRCONC: PORTC Slew Rate Control Register Register 13-25: INLVLC: PORTC Input Level Control Register TABLE 13-8: Summary of Registers Associated with PORTC 13.9 PORTD Registers (PIC16(L)F1789 only) 13.9.1 Data Register 13.9.2 Direction Control 13.9.3 Open-Drain Control 13.9.4 Slew Rate Control 13.9.5 Input Threshold Control 13.9.6 PORTD Functions and Output Priorities TABLE 13-9: PORTD Output Priority 13.10 Register Definitions: PORTD Register 13-26: PORTD: PORTD Register Register 13-27: TRISD: PORTD Tri-State Register Register 13-28: LATD: PORTD Data Latch Register Register 13-29: ANSELD: PORTD Analog Select Register Register 13-30: WPUD: Weak Pull-Up PORTD Register Register 13-31: ODCOND: PORTD Open-Drain Control Register Register 13-32: SLRCOND: PORTD Slew Rate Control Register Register 13-33: INLVLD: PORTD Input Level Control Register TABLE 13-10: Summary of Registers Associated with PORTD 13.11 PORTE Registers 13.11.1 Data Register 13.11.2 Direction Control 13.11.3 Open-Drain Control 13.11.4 Slew Rate Control 13.11.5 Input Threshold Control 13.11.6 Input Threshold Control 13.11.7 PORTE Functions and Output Priorities(1) TABLE 13-11: PORTE Output Priority 13.12 Register Definitions: PORTE Register 13-34: PORTE: PORTE Register Register 13-35: TRISE: PORTE Tri-State Register Register 13-36: LATE: PORTE Data Latch Register(2) Register 13-37: ANSELE: PORTE Analog Select Register(2) Register 13-38: WPUE: Weak Pull-Up PORTE Register Register 13-39: ODCONE: PORTE Open-Drain Control Register(1) Register 13-40: SLRCONE: PORTE Slew Rate Control Register(1) Register 13-41: INLVLE: PORTE Input Level Control Register TABLE 13-12: Summary of Registers Associated with PORTE 14.0 Interrupt-On-Change 14.1 Enabling the Module 14.2 Individual Pin Configuration 14.3 Interrupt Flags 14.4 Clearing Interrupt Flags EXAMPLE 14-1: Clearing Interrupt Flags (PORTA Example) 14.5 Operation in Sleep FIGURE 14-1: Interrupt-On-Change Block Diagram 14.6 Register Definitions: Interrupt-on-Change Control Register 14-1: IOCxP: Interrupt-On-Change Positive Edge Register Register 14-2: IOCxN: Interrupt-On-Change Negative Edge Register Register 14-3: IOCxF: Interrupt-On-Change Flag Register TABLE 14-1: Summary of Registers Associated with Interrupt-On-Change 15.0 Fixed Voltage Reference (FVR) 15.1 Independent Gain Amplifiers 15.2 FVR Stabilization Period 15.3 FVR Buffer Stabilization Period FIGURE 15-1: Voltage Reference Block Diagram TABLE 15-1: Peripherals Requiring the Fixed Voltage Reference (FVR) 15.4 Register Definitions: FVR Control Register 15-1: FVRCON: Fixed Voltage Reference Control Register TABLE 15-2: Summary of Registers Associated with Fixed Voltage Reference 16.0 Temperature Indicator Module 16.1 Circuit Operation EQUATION 16-1: Vout Ranges FIGURE 16-1: Temperature Circuit Diagram 16.2 Minimum Operating Vdd TABLE 16-1: Recommended Vdd vs. Range 16.3 Temperature Output 16.4 ADC Acquisition Time TABLE 16-2: Summary of Registers Associated with the Temperature Indicator 17.0 Analog-to-Digital Converter (ADC) Module FIGURE 17-1: ADC Block Diagram 17.1 ADC Configuration 17.1.1 Port Configuration 17.1.2 Channel Selection 17.1.3 ADC Voltage Reference 17.1.4 Conversion Clock TABLE 17-1: ADC Clock Period (Tad) Vs. Device Operating Frequencies FIGURE 17-2: Analog-to-Digital Conversion Tad Cycles 17.1.5 Interrupts 17.1.6 Result Formatting FIGURE 17-3: ADC Conversion Result Format TABLE 17-2: ADC Output results Format 17.2 ADC Operation 17.2.1 Starting a Conversion 17.2.2 Completion of a Conversion 17.2.3 Terminating a conversion 17.2.4 ADC Operation During Sleep 17.2.5 Auto-Conversion Trigger 17.2.6 A/D Conversion Procedure EXAMPLE 17-1: A/D Conversion 17.3 Register Definitions: ADC Control Register 17-1: ADCON0: ADC Control Register 0 Register 17-2: ADCON1: ADC Control Register 1 Register 17-3: ADCON2: ADC Control Register 2 Register 17-4: ADRESH: ADC Result Register High (ADRESH) ADFM = 0 Register 17-5: ADRESL: ADC Result Register Low (ADRESL) ADFM = 0 Register 17-6: ADRESH: ADC Result Register High (ADRESH) ADFM = 1 Register 17-7: ADRESL: ADC Result Register Low (ADRESL) ADFM = 1 17.4 ADC Acquisition Requirements EQUATION 17-1: Acquisition Time Example FIGURE 17-4: Analog Input Model FIGURE 17-5: ADC Transfer Function TABLE 17-3: Summary of Registers Associated with ADC 18.0 Operational Amplifier (OPA) Modules FIGURE 18-1: OPAx Module Block Diagram 18.1 Effects of Reset 18.2 OPA Module Performance 18.3 OPAxCON Control Register 18.4 Register Definitions: Op Amp Control Register 18-1: OPAxCON: Operational Amplifiers (OPAx) Control Registers TABLE 18-1: Summary of Registers Associated with Op Amps 19.0 8-Bit Digital-to-Analog Converter (DAC) Module 19.1 Output Voltage Selection EQUATION 19-1: DAC Output Voltage 19.2 Ratiometric Output Level 19.3 DAC Voltage Reference Output FIGURE 19-1: Digital-to-Analog Converter Block Diagram FIGURE 19-2: Voltage Reference Output Buffer Example 19.4 Operation During Sleep 19.5 Effects of a Reset 19.6 Register Definitions: DAC Control Register 19-1: DAC1CON0: Voltage Reference Control Register 0 Register 19-2: DAC1CON1: Voltage Reference Control Register 1 TABLE 19-1: Summary of Registers Associated with the DAC Module 20.0 5-bit Digital-to-Analog Converter (DAC2/3/4) Modules 20.1 Output Voltage Selection EQUATION 20-1: DAC Output Voltage 20.2 Ratiometric Output Level 20.3 DAC Voltage Reference Output FIGURE 20-1: Digital-to-Analog Converter Block Diagram FIGURE 20-2: Voltage Reference Output Buffer Example 20.4 Operation During Sleep 20.5 Effects of a Reset 20.6 Register Definitions: DACx Control Register 20-1: DACxCON0: Voltage Reference Control Register 0 Register 20-2: DACxCON1: Voltage Reference Control Register 1 TABLE 20-1: Summary of Registers Associated with the DAC2/3/4 Modules 21.0 Comparator Module 21.1 Comparator Overview TABLE 21-1: Comparator Availability Per Device FIGURE 21-1: Single Comparator FIGURE 21-2: Comparator Module Simplified Block Diagram 21.2 Comparator Control 21.2.1 Comparator Enable 21.2.2 Comparator Output Selection 21.2.3 Comparator Output Polarity TABLE 21-2: Comparator Output State vs. Input Conditions 21.2.4 Comparator Speed/Power Selection 21.3 Comparator Hysteresis 21.4 Timer1 Gate Operation 21.4.1 Comparator Output Synchronization 21.5 Comparator Interrupt 21.6 Comparator Positive Input Selection 21.7 Comparator Negative Input Selection 21.8 Comparator Response Time 21.9 Zero Latency Filter FIGURE 21-3: Comparator Zero Latency Filter Operation 21.10 Analog Input Connection Considerations 21.10.1 Alternate Pin Locations FIGURE 21-4: Analog Input Model 21.11 Register Definitions: Comparator Control Register 21-1: CMxCON0: Comparator Cx Control Register 0 Register 21-2: CMxCON1: Comparator Cx Control Register 1 Register 21-3: CMOUT: Comparator Output Register TABLE 21-3: Summary of Registers Associated with Comparator Module 22.0 Timer0 Module 22.1 Timer0 Operation 22.1.1 8-bit Timer Mode 22.1.2 8-bit Counter Mode FIGURE 22-1: Block Diagram of the Timer0 22.1.3 Software Programmable Prescaler 22.1.4 Timer0 Interrupt 22.1.5 8-bit Counter Mode Synchronization 22.1.6 Operation During Sleep 22.2 Register Definitions: Option Register Register 22-1: OPTION_REG: OPTION Register TABLE 22-1: Summary of Registers Associated with Timer0 23.0 Timer1 Module with Gate Control FIGURE 23-1: Timer1 Block Diagram 23.1 Timer1 Operation TABLE 23-1: Timer1 Enable Selections 23.2 Clock Source Selection 23.2.1 Internal Clock Source 23.2.2 External Clock Source TABLE 23-2: Clock Source Selections 23.3 Timer1 Prescaler 23.4 Timer1 Oscillator 23.5 Timer1 Operation in Asynchronous Counter Mode 23.5.1 Reading and Writing Timer1 in Asynchronous Counter Mode 23.6 Timer1 Gate 23.6.1 Timer1 Gate Enable TABLE 23-3: Timer1 Gate Enable Selections 23.6.2 Timer1 Gate Source Selection TABLE 23-4: Timer1 Gate Sources 23.6.3 Timer1 Gate Toggle Mode 23.6.4 Timer1 Gate Single-Pulse Mode 23.6.5 Timer1 Gate Value 23.6.6 Timer1 Gate Event Interrupt 23.7 Timer1 Interrupt 23.8 Timer1 Operation During Sleep 23.9 CCP Capture/Compare Time Base 23.10 CCP Auto-Conversion Trigger FIGURE 23-2: Timer1 Incrementing Edge FIGURE 23-3: Timer1 Gate Enable Mode FIGURE 23-4: Timer1 Gate Toggle Mode FIGURE 23-5: Timer1 Gate Single-Pulse Mode FIGURE 23-6: Timer1 Gate Single-Pulse and Toggle Combined Mode 23.11 Register Definitions: Timer1 Control Register 23-1: T1CON: Timer1 Control Register Register 23-2: T1GCON: Timer1 Gate Control Register TABLE 23-5: Summary of Registers Associated with Timer1 24.0 Timer2 Module FIGURE 24-1: Timer2 Block Diagram 24.1 Timer2 Operation 24.2 Timer2 Interrupt 24.3 Timer2 Output 24.4 Timer2 Operation During Sleep 24.5 Register Definitions: Timer2 Control Register 24-1: T2CON: Timer2 Control Register TABLE 24-1: Summary of Registers Associated with Timer2 25.0 Capture/Compare/PWM Modules 25.1 Capture Mode 25.1.1 CCP Pin Configuration FIGURE 25-1: Capture Mode Operation Block Diagram 25.1.2 Timer1 Mode Resource 25.1.3 Software Interrupt Mode 25.1.4 CCP Prescaler EXAMPLE 25-1: Changing Between Capture Prescalers 25.1.5 Capture During Sleep 25.1.6 Alternate Pin Locations 25.2 Compare Mode FIGURE 25-2: Compare Mode Operation Block Diagram 25.2.1 CCPx Pin Configuration 25.2.2 Timer1 Mode Resource 25.2.3 Software Interrupt Mode 25.2.4 Auto-Conversion Trigger 25.2.5 Compare During Sleep 25.2.6 Alternate Pin Locations 25.3 PWM Overview 25.3.1 Standard PWM Operation FIGURE 25-3: CCP PWM Output Signal FIGURE 25-4: Simplified PWM Block Diagram 25.3.2 Setup for PWM Operation 25.3.3 Timer2 Timer Resource 25.3.4 PWM Period EQUATION 25-1: PWM Period 25.3.5 PWM Duty Cycle EQUATION 25-2: Pulse Width EQUATION 25-3: Duty Cycle Ratio 25.3.6 PWM Resolution EQUATION 25-4: PWM Resolution TABLE 25-1: Example PWM Frequencies and Resolutions (Fosc = 20 MHz) TABLE 25-2: Example PWM Frequencies and Resolutions (Fosc = 8 MHz) 25.3.7 Operation in Sleep Mode 25.3.8 Changes in System Clock Frequency 25.3.9 Effects of Reset TABLE 25-3: Summary of Registers Associated with Standard PWM 25.4 Register Definitions: CCP Control Register 25-1: CCPXCON: CCPx Control Register 26.0 Programmable Switch Mode Control (PSMC) FIGURE 26-1: PSMC Simplified Block Diagram 26.1 Fundamental Operation FIGURE 26-2: Basic PWM Waveform Generation 26.1.1 Period Event 26.1.2 Rising Edge Event 26.1.3 Falling Edge Event 26.2 Event Sources 26.2.1 Time Base EQUATION 26-1: PWM Period EQUATION 26-2: PWM Duty Cycle 26.2.2 0% Duty Cycle Operation Using Time Base 26.2.3 100% Duty Cycle Operation Using Time Base 26.2.4 Time Base Interrupt Generation 26.2.5 PSMC Time Base Clock Sources 26.2.6 Clock Prescaler FIGURE 26-3: Time Base Waveform Generation 26.2.7 Asynchronous Inputs 26.2.8 Input Blanking 26.2.9 Output Waveform Generation 26.2.10 Output Control 26.3 Modes of Operation 26.3.1 Single-Phase Mode EXAMPLE 26-1: Single-Phase Setup FIGURE 26-4: Single PWM Waveform – PSMCxSTR0 = 01h 26.3.2 Complementary PWM EXAMPLE 26-2: Complementary Single-Phase Setup FIGURE 26-5: Complementary PWM Waveform – PSMCxSTR0 = 03h 26.3.3 Push-Pull PWM EXAMPLE 26-3: Push-Pull Setup FIGURE 26-6: Push-Pull PWM Waveform 26.3.4 Push-Pull PWM with Complementary Outputs FIGURE 26-7: Push-Pull with Complementary Outputs PWM Waveform 26.3.5 Push-Pull PWM with Four Full-Bridge Outputs FIGURE 26-8: Push-Pull PWM with 4 Full-Bridge Outputs 26.3.6 Push-Pull PWM with Four Full-Bridge and Complementary Outputs FIGURE 26-9: Push-Pull 4 Full-Bridge and Complementary PWM 26.3.7 Pulse-Skipping PWM FIGURE 26-10: Pulse-Skipping PWM Waveform 26.3.8 Pulse-Skipping PWM with Complementary Outputs FIGURE 26-11: Pulse-Skipping with Complementary Output PWM Waveform 26.3.9 ECCP Compatible Full-Bridge PWM FIGURE 26-12: ECCP Compatible Full-Bridge PWM Waveform – PSMCxSTR0 = 0Fh 26.3.10 Variable Frequency – Fixed Duty Cycle PWM FIGURE 26-13: Variable Frequency – Fixed Duty Cycle PWM Waveform 26.3.11 Variable Frequency - Fixed Duty Cycle PWM with Complementary Outputs FIGURE 26-14: Variable Frequency – Fixed Duty Cycle PWM with Complementary Outputs Waveform 26.3.12 3-Phase PWM TABLE 26-1: Phase Grouping TABLE 26-2: 3-phase Steering Control FIGURE 26-15: 3-phase PWM Steering Waveform (PxHSMEN = 0 and PxLSMEN = 1) 26.4 Dead-Band Control 26.4.1 Dead-band Types 26.4.2 Dead-band Enable 26.4.3 Dead-band Clock source 26.4.4 Dead-band Uncertainty 26.4.5 Dead-band Overlap 26.5 Output Steering 26.5.1 3-phase Steering 26.5.2 Single PWM Steering FIGURE 26-16: Single PWM Steering Waveform (No Synchronization) 26.5.3 Complementary PWM Steering FIGURE 26-17: Complementary PWM Steering Waveform (No Synchronization, Zero Dead-Band Time) 26.5.4 Synchronized PWM Steering 26.5.5 Initializing Synchronized Steering FIGURE 26-18: PWM Steering with Synchronization Waveform 26.6 PSMC Modulation (Burst Mode) 26.6.1 Modulation Enable 26.6.2 Modulation Sources 26.6.3 Modulation Effect on PWM Signals FIGURE 26-19: PSMC Modulation Waveform 26.7 Auto-Shutdown 26.7.1 Shutdown 26.7.2 Pin Override Levels 26.7.3 Restart from Auto-Shutdown FIGURE 26-20: Auto-Shutdown and Restart Waveform 26.8 PSMC Synchronization 26.8.1 Synchronization Sources FIGURE 26-21: PSMC Synchronization - Sync Output to Pin 26.9 Fractional Frequency Adjust (FFA) FIGURE 26-22: FFA Block Diagram. TABLE 26-3: Fractional Frequency Adjust Calculations TABLE 26-4: Sample FFA Output Periods/Frequencies 26.10 Register Updates 26.10.1 Double Buffered Registers 26.10.2 Module Disabled Updates 26.10.3 Module Enabled Updates 26.11 Operation During Sleep 26.12 Register Definitions: PSMC Control Register 26-1: PSMCxCON: PSMC Control Register Register 26-2: PSMCxMDL: PSMC Modulation Control Register Register 26-3: PSMC1SYNC: PSMC1 Synchronization Control Register Register 26-4: PSMC2SYNC: PSMC2 Synchronization Control Register Register 26-5: PSMC3SYNC: PSMC3 Synchronization Control Register Register 26-6: PSMC4SYNC: PSMC3 Synchronization Control Register Register 26-7: PSMCxCLK: PSMC Clock Control Register Register 26-8: PSMCxOEN: PSMC Output Enable Control Register Register 26-9: PSMCxPOL: PSMC Polarity Control Register Register 26-10: PSMCxBLNK: PSMC Blanking Control Register Register 26-11: PSMCxREBS: PSMC Rising Edge Blanked Source Register Register 26-12: PSMCxFEBS: PSMC Falling Edge Blanked Source Register Register 26-13: PSMCxPHS: PSMC Phase Source Register(1) Register 26-14: PSMCxDCS: PSMC Duty Cycle Source Register(1) Register 26-15: PSMCxPRS: PSMC Period Source Register(1) Register 26-16: PSMCxASDC: PSMC Auto-Shutdown Control Register Register 26-17: PSMCxASDL: PSMC Auto-Shutdown Output Level Register Register 26-18: PSMCxASDS: PSMC Auto-Shutdown Source Register Register 26-19: PSMCxTMRL: PSMC Time Base Counter Low Register Register 26-20: PSMCxTMRH: PSMC Time Base Counter High Register Register 26-21: PSMCxPHL: PSMC Phase Count Low Byte Register Register 26-22: PSMCxPHH: PSMC Phase Count High Byte Register Register 26-23: PSMCxDCL: PSMC Duty Cycle Count Low Byte Register Register 26-24: PSMCxDCH: PSMC Duty Cycle Count High Register Register 26-25: PSMCxPRL: PSMC Period Count Low Byte Register Register 26-26: PSMCxPRH: PSMC Period Count High Byte Register Register 26-27: PSMCxDBR: PSMC Rising Edge Dead-Band Time Register Register 26-28: PSMCxDBF: PSMC Falling Edge Dead-Band Time Register Register 26-29: PSMCxFFA: PSMC Fractional Frequency Adjust Register Register 26-30: PSMCxBLKR: PSMC Rising Edge Blanking Time Register Register 26-31: PSMCxBLKF: PSMC Falling Edge Blanking Time Register Register 26-32: PSMCxSTR0: PSMC Steering Control Register 0 Register 26-33: PSMCxSTR1: PSMC Steering Control Register 1 Register 26-34: PSMCxINT: PSMC Time Base Interrupt Control Register TABLE 26-5: Summary of Registers Associated with PSMC 27.0 Master Synchronous Serial Port (MSSP) Module 27.1 Master SSP (MSSP) Module Overview FIGURE 27-1: MSSP Block Diagram (SPI mode) FIGURE 27-2: MSSP Block Diagram (I2C Master mode) FIGURE 27-3: MSSP Block Diagram (I2C Slave mode) 27.2 SPI Mode Overview FIGURE 27-4: SPI Master and Multiple Slave Connection 27.2.1 SPI Mode Registers 27.2.2 SPI Mode Operation FIGURE 27-5: SPI Master/Slave Connection 27.2.3 SPI Master Mode FIGURE 27-6: SPI Mode Waveform (Master Mode) 27.2.4 SPI Slave Mode 27.2.5 Slave Select Synchronization FIGURE 27-7: SPI Daisy-Chain Connection FIGURE 27-8: Slave Select Synchronous Waveform FIGURE 27-9: SPI Mode Waveform (Slave Mode with CKE = 0) FIGURE 27-10: SPI Mode Waveform (Slave Mode with CKE = 1) 27.2.6 SPI Operation in Sleep Mode TABLE 27-1: Summary of Registers Associated with SPI Operation 27.3 I2C Mode Overview FIGURE 27-11: I2C Master/ Slave Connection 27.3.1 Clock Stretching 27.3.2 Arbitration 27.4 I2C Mode Operation 27.4.1 Byte Format 27.4.2 Definition of I2C Terminology 27.4.3 SDA and SCL Pins 27.4.4 SDA Hold Time TABLE 27-2: I2C Bus terms 27.4.5 Start Condition 27.4.6 Stop Condition 27.4.7 Restart Condition 27.4.8 Start/Stop Condition Interrupt Masking FIGURE 27-12: I2C Start and Stop Conditions FIGURE 27-13: I2C Restart Condition 27.4.9 Acknowledge Sequence 27.5 I2C Slave Mode Operation 27.5.1 Slave Mode Addresses 27.5.2 Slave Reception FIGURE 27-14: I2C Slave, 7-bit Address, Reception (SEN = 0, AHEN = 0, DHEN = 0) FIGURE 27-15: I2C Slave, 7-bit Address, Reception (SEN = 1, AHEN = 0, DHEN = 0) FIGURE 27-16: I2C Slave, 7-bit Address, Reception (SEN = 0, AHEN = 1, DHEN = 1) FIGURE 27-17: I2C Slave, 7-bit Address, Reception (SEN = 1, AHEN = 1, DHEN = 1) 27.5.3 Slave Transmission FIGURE 27-18: I2C Slave, 7-bit Address, Transmission (AHEN = 0) FIGURE 27-19: I2C Slave, 7-bit Address, Transmission (AHEN = 1) 27.5.4 Slave Mode 10-bit Address Reception 27.5.5 10-bit Addressing with Address or Data Hold FIGURE 27-20: I2C Slave, 10-bit Address, Reception (SEN = 1, AHEN = 0, DHEN = 0) FIGURE 27-21: I2C Slave, 10-bit Address, Reception (SEN = 0, AHEN = 1, DHEN = 0) FIGURE 27-22: I2C Slave, 10-bit Address, Transmission (SEN = 0, AHEN = 0, DHEN = 0) 27.5.6 Clock Stretching 27.5.7 Clock Synchronization and the CKP bit FIGURE 27-23: Clock Synchronization Timing 27.5.8 General Call Address Support FIGURE 27-24: Slave Mode General Call Address Sequence 27.5.9 SSP Mask Register 27.6 I2C Master Mode 27.6.1 I2C Master Mode Operation 27.6.2 Clock Arbitration FIGURE 27-25: Baud Rate Generator Timing with Clock Arbitration 27.6.3 WCOL Status Flag 27.6.4 I2C Master Mode Start Condition Timing FIGURE 27-26: First Start Bit Timing 27.6.5 I2C Master Mode Repeated Start Condition Timing FIGURE 27-27: Repeat Start Condition Waveform 27.6.6 I2C Master Mode Transmission FIGURE 27-28: I2C Master Mode Waveform (Transmission, 7 or 10-bit Address) 27.6.7 I2C Master Mode Reception FIGURE 27-29: I2C Master Mode Waveform (Reception, 7-bit Address) 27.6.8 Acknowledge Sequence Timing 27.6.9 Stop Condition Timing FIGURE 27-30: Acknowledge Sequence Waveform FIGURE 27-31: Stop Condition Receive or Transmit Mode 27.6.10 Sleep Operation 27.6.11 Effects of a Reset 27.6.12 Multi-Master Mode 27.6.13 Multi -Master Communication, Bus Collision and Bus Arbitration FIGURE 27-32: Bus Collision Timing for Transmit and Acknowledge FIGURE 27-33: Bus Collision During Start Condition (SDA Only) FIGURE 27-34: Bus Collision During Start Condition (SCL = 0) FIGURE 27-35: BRG Reset Due to SDA Arbitration During Start Condition FIGURE 27-36: Bus Collision During a Repeated Start Condition (Case 1) FIGURE 27-37: Bus Collision During Repeated Start Condition (Case 2) FIGURE 27-38: Bus Collision During a Stop Condition (Case 1) FIGURE 27-39: Bus Collision During a Stop Condition (Case 2) TABLE 27-3: Summary of Registers Associated with I2C Operation 27.7 Baud Rate Generator FIGURE 27-40: Baud Rate Generator Block Diagram TABLE 27-4: MSSP Clock Rate w/BRG 27.8 Register Definitions: MSSP Control Register 27-1: SSPSTAT: SSP STATUS Register Register 27-2: SSPCON1: SSP Control Register 1 Register 27-3: SSPCON2: SSP Control Register 2 Register 27-4: SSPCON3: SSP Control Register 3 Register 27-5: SSPMSK: SSP Mask Register Register 27-6: SSPADD: MSSP Address and Baud Rate Register (I2C Mode) 28.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) FIGURE 28-1: EUSART Transmit Block Diagram FIGURE 28-2: EUSART Receive Block Diagram 28.1 EUSART Asynchronous Mode 28.1.1 EUSART Asynchronous Transmitter FIGURE 28-3: Asynchronous Transmission FIGURE 28-4: Asynchronous Transmission (Back-to-Back) TABLE 28-1: Summary of Registers Associated with Asynchronous Transmission 28.1.2 EUSART Asynchronous Receiver FIGURE 28-5: Asynchronous Reception TABLE 28-2: Summary of Registers Associated with Asynchronous Reception 28.2 Clock Accuracy with Asynchronous Operation 28.3 Register Definitions: EUSART Control Register 28-1: TXSTA: Transmit Status and Control Register Register 28-2: RCSTA: Receive Status and Control Register Register 28-3: BAUDCON: Baud Rate Control Register 28.4 EUSART Baud Rate Generator (BRG) EXAMPLE 28-1: Calculating Baud Rate Error TABLE 28-3: Baud Rate Formulas TABLE 28-4: Summary of Registers Associated with the Baud Rate Generator TABLE 28-5: BAUD Rates for Asynchronous Modes 28.4.1 Auto-Baud Detect TABLE 28-6: BRG Counter Clock Rates FIGURE 28-6: Automatic Baud Rate Calibration 28.4.2 Auto-Baud Overflow 28.4.3 Auto-Wake-up on Break FIGURE 28-7: Auto-Wake-up bit (WUE) Timing During Normal Operation FIGURE 28-8: Auto-Wake-up Bit (WUE) Timings During Sleep 28.4.4 Break Character Sequence 28.4.5 Receiving a Break Character FIGURE 28-9: Send Break Character Sequence 28.5 EUSART Synchronous Mode 28.5.1 Synchronous Master Mode FIGURE 28-10: Synchronous Transmission FIGURE 28-11: Synchronous Transmission (Through TXEN) TABLE 28-7: Summary of Registers Associated with Synchronous Master Transmission FIGURE 28-12: Synchronous Reception (Master Mode, SREN) TABLE 28-8: Summary of Registers Associated with Synchronous Master Reception 28.5.2 Synchronous Slave Mode TABLE 28-9: Summary of Registers Associated with Synchronous Slave Transmission TABLE 28-10: Summary of Registers Associated with Synchronous Slave Reception 28.6 EUSART Operation During Sleep 28.6.1 Synchronous Receive During Sleep 28.6.2 Synchronous Transmit During Sleep 28.6.3 Alternate Pin Locations 29.0 In-Circuit Serial Programming™ (ICSP™) 29.1 High-Voltage Programming Entry Mode 29.2 Low-Voltage Programming Entry Mode 29.3 Common Programming Interfaces FIGURE 29-1: ICD RJ-11 Style Connector Interface FIGURE 29-2: PICkit™ Programmer Style Connector Interface FIGURE 29-3: Typical Connection for ICSP™ Programming 30.0 Instruction Set Summary 30.1 Read-Modify-Write Operations TABLE 30-1: Opcode Field Descriptions TABLE 30-2: Abbreviation Descriptions FIGURE 30-1: General Format for Instructions TABLE 30-3: Enhanced Mid-Range Instruction Set TABLE 30-4: Enhanced Mid-Range Instruction Set (Continued) 30.2 Instruction Descriptions 31.0 Electrical Specifications 31.1 Absolute Maximum Ratings(†) 31.2 Standard Operating Conditions FIGURE 31-1: PIC16F1788/9 Voltage Frequency Graph, -40°C £ Ta £ +125°C FIGURE 31-2: PIC16LF1788/9 Voltage Frequency Graph, -40°C £ Ta £ +125°C 31.3 DC Characteristics TABLE 31-1: Supply Voltage FIGURE 31-3: POR and POR Rearm with Slow Rising Vdd TABLE 31-2: Supply Voltage (Idd)(1,2) TABLE 31-3: Power-Down Currents (Ipd)(1,2,4) TABLE 31-4: I/O Ports TABLE 31-5: Memory Programming Requirements 31.4 Thermal Considerations 31.5 AC Characteristics FIGURE 31-4: Load Conditions FIGURE 31-5: Clock Timing TABLE 31-6: Clock Oscillator Timing Requirements TABLE 31-7: Oscillator Parameters FIGURE 31-6: HFINTOSC Frequency Accuracy Over Device Vdd and Temperature TABLE 31-8: PLL Clock Timing Specifications FIGURE 31-7: CLKOUT and I/O Timing TABLE 31-9: CLKOUT and I/O Timing Parameters FIGURE 31-8: Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Timing FIGURE 31-9: Brown-Out Reset Timing and Characteristics TABLE 31-10: Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer and Brown-Out Reset Parameters FIGURE 31-10: Timer0 and Timer1 External Clock Timings TABLE 31-11: Timer0 and Timer1 External Clock Requirements FIGURE 31-11: Capture/Compare/PWM Timings (CCP) TABLE 31-12: Capture/Compare/PWM Requirements (CCP) TABLE 31-13: ADC Converter (ADC) 12-Bit Differential Characteristics: TABLE 31-14: ADC Conversion Requirements FIGURE 31-12: ADC Conversion Timing (Normal Mode) FIGURE 31-13: ADC Conversion Timing (Sleep Mode) TABLE 31-15: Operational Amplifier (OPA) TABLE 31-16: Comparator Specifications TABLE 31-17: 5-Bit Digital-to-Analog Converter (DAC) Specifications TABLE 31-18: 8-Bit Digital-to-Analog Converter (DAC) Specifications FIGURE 31-14: EUSART Synchronous Transmission (Master/Slave) Timing TABLE 31-19: EUSART Synchronous Transmission Requirements FIGURE 31-15: EUSART Synchronous Receive (Master/Slave) Timing TABLE 31-20: EUSART Synchronous Receive Requirements FIGURE 31-16: SPI Master Mode Timing (CKE = 0, SMP = 0) FIGURE 31-17: SPI Master Mode Timing (CKE = 1, SMP = 1) FIGURE 31-18: SPI Slave Mode Timing (CKE = 0) FIGURE 31-19: SPI Slave Mode Timing (CKE = 1) TABLE 31-21: SPI Mode requirements FIGURE 31-20: I2C Bus Start/Stop Bits Timing TABLE 31-22: I2C Bus Start/Stop Bits Requirements FIGURE 31-21: I2C Bus Data Timing TABLE 31-23: I2C Bus Data Requirements 32.0 DC and AC Characteristics Graphs and Charts 33.0 Development Support 33.1 MPLAB X Integrated Development Environment Software 33.2 MPLAB XC Compilers 33.3 MPASM Assembler 33.4 MPLINK Object Linker/ MPLIB Object Librarian 33.5 MPLAB Assembler, Linker and Librarian for Various Device Families 33.6 MPLAB X SIM Software Simulator 33.7 MPLAB REAL ICE In-Circuit Emulator System 33.8 MPLAB ICD 3 In-Circuit Debugger System 33.9 PICkit 3 In-Circuit Debugger/ Programmer 33.10 MPLAB PM3 Device Programmer 33.11 Demonstration/Development Boards, Evaluation Kits, and Starter Kits 33.12 Third-Party Development Tools 34.0 Packaging Information 34.1 Package Marking Information Package Marking Information (Continued) Package Marking Information (Continued) 34.2 Package Details Appendix A: Data Sheet Revision History The Microchip Website Customer Change Notification Service Customer Support Product Identification System