Datasheet ATmega64A - Summary (Microchip) - 8

HerstellerMicrochip
Beschreibung8-bit AVR Micrcontroller
Seiten / Seite20 / 8 — ATmega103 and ATmega64A Compatibility. 5.1. ATmega103 Compatibility Mode
Dateiformat / GrößePDF / 333 Kb
DokumentenspracheEnglisch

ATmega103 and ATmega64A Compatibility. 5.1. ATmega103 Compatibility Mode

ATmega103 and ATmega64A Compatibility 5.1 ATmega103 Compatibility Mode

Modelllinie für dieses Datenblatt

Textversion des Dokuments

5. ATmega103 and ATmega64A Compatibility
The ATmega64A is a highly complex microcontroller where the number of I/O locations supersedes the 64 I/O locations reserved in the AVR instruction set. To ensure backward compatibility with the ATmega103, all I/O locations present in ATmega103 have the same location in ATmega64A. Most additional I/O locations are added in an Extended I/O space starting from 0x60 to 0xFF, (that is, in the ATmega103 internal RAM space). These locations can be reached by using LD/LDS/LDD and ST/STS/STD instructions only, not by using IN and OUT instructions. The relocation of the internal RAM space may still be a problem for ATmega103 users. Also, the increased number of interrupt vectors might be a problem if the code uses absolute addresses. To solve these problems, an ATmega103 compatibility mode can be selected by programming the fuse M103C. In this mode, none of the functions in the Extended I/O space are in use, so the internal RAM is located as in ATmega103. Also, the Extended Interrupt vectors are removed. The Atmel AVR ATmega64A is 100% pin compatible with ATmega103, and can replace the ATmega103 on current Printed Circuit Boards. The application note “Replacing ATmega103 by ATmega64A” describes what the user should be aware of replacing the ATmega103 by an ATmega64A.
5.1. ATmega103 Compatibility Mode
By programming the M103C fuse, the ATmega64A will be compatible with the ATmega103 regards to RAM, I/O pins and interrupt vectors as described above. However, some new features in ATmega64A are not available in this compatibility mode, these features are listed below: • One USART instead of two, Asynchronous mode only. Only the eight least significant bits of the Baud Rate Register is available. • One 16 bits Timer/Counter with two compare registers instead of two 16-bit Timer/Counters with three compare registers. • Two-wire serial interface is not supported. • Port C is output only. • Port G serves alternate functions only (not a general I/O port). • Port F serves as digital input only in addition to analog input to the ADC. • Boot Loader capabilities is not supported. • It is not possible to adjust the frequency of the internal calibrated RC Oscillator. • The External Memory Interface can not release any Address pins for general I/O, neither configure different wait-states to different External Memory Address sections. • In addition, there are some other minor differences to make it more compatible to ATmega103: • Only EXTRF and PORF exists in MCUCSR. • Timed sequence not required for Watchdog Time-out change. • External Interrupt pins 3 - 0 serve as level interrupt only. • USART has no FIFO buffer, so data overrun comes earlier. Unused I/O bits in ATmega103 should be written to 0 to ensure same operation in ATmega64A. Atmel ATmega64A [DATASHEET] 8 Atmel-8160ES-8-bit AVR Micrcontroller_Datasheet_Summary-09/2015 Document Outline Introduction Features Table of Contents 1. Description 2. Configuration Summary 3. Ordering Information 4. Block Diagram 5. ATmega103 and ATmega64A Compatibility 5.1. ATmega103 Compatibility Mode 6. Pin Configurations 6.1. Pin Descriptions 6.1.1. VCC 6.1.2. GND 6.1.3. Port A (PA7:PA0) 6.1.4. Port B (PB7:PB0) 6.1.5. Port C (PC7:PC0) 6.1.6. Port D (PD7:PD0) 6.1.7. Port E (PE7:PE0) 6.1.8. Port F (PF7:PF0) 6.1.9. Port G (PG4:PG0) 6.1.10. RESET 6.1.11. XTAL1 6.1.12. XTAL2 6.1.13. AVCC 6.1.14. AREF 6.1.15. PEN 7. Resources 8. Data Retention 9. About Code Examples 10. Capacitive Touch Sensing 11. Packaging Information 11.1. 64A 11.2. 64M1 12. Errata 12.1. ATmega64A Rev. D