Datasheet ATmega64A - Summary (Microchip) - 4

1. Description
The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. The ATmega64A provides the following features: 64 Kbytes In-System Programmable Flash with Read- While- Write capabilities, 2 Kbytes EEPROM, 4 Kbytes SRAM, 53 general purpose I/O lines, 32 general purpose working registers, Real Time Counter (RTC), four flexible Timer/Counters with compare modes and PWM, two USARTs, a byte oriented Two-wire Serial Interface, an 8-channel, 10-bit ADC with optional differential input stage with programmable gain, programmable Watchdog Timer with internal Oscillator, an SPI serial port, IEEE std. 1149.1 compliant JTAG test interface, also used for accessing the On-chip Debug system and programming, and six software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next interrupt or Hardware Reset. In Power-save mode, the asynchronous timer continues to run, allowing the user to maintain a timer base while the rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O modules except asynchronous timer and ADC, to minimize switching noise during ADC conversions. In Standby mode, the crystal/resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low power consumption. In Extended Standby mode, both the main Oscillator and the asynchronous timer continue to run. The device is manufactured using Atmel’s high-density non-volatile memory technology. The On-chip ISP Flash allows the program memory to be reprogrammed In-System through an SPI serial interface, by a conventional nonvolatile memory programmer, or by an On-chip Boot program running on the AVR core. The Boot Program can use any interface to download the Application Program in the Application Flash memory. Software in the Boot Flash section will continue to run while the Application Flash section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATmega64A is a powerful microcontroller that provides a highly-flexible and cost-effective solution to many embedded control applications. The ATmega64A AVR is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits. Atmel ATmega64A [DATASHEET] 4 Atmel-8160ES-8-bit AVR Micrcontroller_Datasheet_Summary-09/2015 Document Outline Introduction Features Table of Contents 1. Description 2. Configuration Summary 3. Ordering Information 4. Block Diagram 5. ATmega103 and ATmega64A Compatibility 5.1. ATmega103 Compatibility Mode 6. Pin Configurations 6.1. Pin Descriptions 6.1.1. VCC 6.1.2. GND 6.1.3. Port A (PA7:PA0) 6.1.4. Port B (PB7:PB0) 6.1.5. Port C (PC7:PC0) 6.1.6. Port D (PD7:PD0) 6.1.7. Port E (PE7:PE0) 6.1.8. Port F (PF7:PF0) 6.1.9. Port G (PG4:PG0) 6.1.10. RESET 6.1.11. XTAL1 6.1.12. XTAL2 6.1.13. AVCC 6.1.14. AREF 6.1.15. PEN 7. Resources 8. Data Retention 9. About Code Examples 10. Capacitive Touch Sensing 11. Packaging Information 11.1. 64A 11.2. 64M1 12. Errata 12.1. ATmega64A Rev. D