Datasheet ATtiny24A, ATtiny44A, ATtiny84A. Complete (Microchip) - 10

link to page 11 X-register 7 0 7 0 R27 (0x1B) R26 (0x1A) 15 YH YL 0 Y-register 7 0 7 0 R29 (0x1D) R28 (0x1C) 15 ZH ZL 0 Z-register 7 0 7 0 R31 (0x1F) R30 (0x1E) In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the instruction set reference for details).
4.5 Stack Pointer
The Stack is mainly used for storing temporary data, for storing local variables and for storing return addresses after interrupts and subroutine calls. The Stack Pointer Register always points to the top of the Stack. Note that the Stack is implemented as growing from higher memory loca- tions to lower memory locations. This implies that a Stack PUSH command decreases the Stack Pointer. The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt Stacks are located. This Stack space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. The Stack Pointer must be set to point above 0x60. The Stack Pointer is decremented by one when data is pushed onto the Stack with the PUSH instruction, and it is decremented by two when the return address is pushed onto the Stack with subroutine call or interrupt. The Stack Pointer is incremented by one when data is popped from the Stack with the POP instruction, and it is incremented by two when data is popped from the Stack with return from subroutine RET or return from interrupt RETI. The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of bits actually used is implementation dependent. Note that the data space in some implementa- tions of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register will not be present.
4.6 Instruction Execution Timing
This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU clock clk , directly generated from the selected clock source for the CPU chip. No internal clock division is used. Figure 4-4 shows the parallel instruction fetches and instruction executions enabled by the Har- vard architecture and the fast access Register File concept. This is the basic pipelining concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost, functions per clocks, and functions per power-unit.
10 ATtiny24A/44A/84A
8183F–AVR–06/12 Document Outline Features 1. Pin Configurations 1.1 Pin Descriptions 1.1.1 VCC 1.1.2 GND 1.1.3 Port B (PB3:PB0) 1.1.4 RESET 1.1.5 Port A (PA7:PA0) 2. Overview 3. General Information 3.1 Resources 3.2 Code Examples 3.3 Capacitive Touch Sensing 3.4 Data Retention 3.5 Disclaimer 4. CPU Core 4.1 Architectural Overview 4.2 ALU – Arithmetic Logic Unit 4.3 Status Register 4.4 General Purpose Register File 4.4.1 The X-register, Y-register, and Z-register 4.5 Stack Pointer 4.6 Instruction Execution Timing 4.7 Reset and Interrupt Handling 4.7.1 Interrupt Response Time 4.8 Register Description 4.8.1 SPH and SPL – Stack Pointer Register 4.8.2 SREG – AVR Status Register 5. Memories 5.1 In-System Re-programmable Flash Program Memory 5.2 SRAM Data Memory 5.2.1 Data Memory Access Times 5.3 EEPROM Data Memory 5.3.1 EEPROM Read/Write Access 5.3.2 Atomic Byte Programming 5.3.3 Split Byte Programming 5.3.4 Erase 5.3.5 Write 5.3.6 Program Examples 5.3.7 Preventing EEPROM Corruption 5.4 I/O Memory 5.4.1 General Purpose I/O Registers 5.5 Register Description 5.5.1 EEARH – EEPROM Address Register 5.5.2 EEARL – EEPROM Address Register 5.5.3 EEDR – EEPROM Data Register 5.5.4 EECR – EEPROM Control Register 5.5.5 GPIOR2 – General Purpose I/O Register 2 5.5.6 GPIOR1 – General Purpose I/O Register 1 5.5.7 GPIOR0 – General Purpose I/O Register 0 6. Clock System 6.1 Clock Subsystems 6.1.1 CPU Clock – clkCPU 6.1.2 I/O Clock – clkI/O 6.1.3 Flash Clock – clkFLASH 6.1.4 ADC Clock – clkADC 6.2 Clock Sources 6.2.1 External Clock 6.2.2 Calibrated Internal 8 MHz Oscillator 6.2.3 Internal 128 kHz Oscillator 6.2.4 Low-Frequency Crystal Oscillator 6.2.5 Crystal Oscillator / Ceramic Resonator 6.2.6 Default Clock Source 6.3 System Clock Prescaler 6.3.1 Switching Time 6.4 Clock Output Buffer 6.5 Register Description 6.5.1 OSCCAL – Oscillator Calibration Register 6.5.2 CLKPR – Clock Prescale Register 7. Power Management and Sleep Modes 7.1 Sleep Modes 7.1.1 Idle Mode 7.1.2 ADC Noise Reduction Mode 7.1.3 Power-Down Mode 7.1.4 Standby Mode 7.2 Software BOD Disable 7.3 Power Reduction Register 7.4 Minimizing Power Consumption 7.4.1 Analog to Digital Converter 7.4.2 Analog Comparator 7.4.3 Brown-out Detector 7.4.4 Internal Voltage Reference 7.4.5 Watchdog Timer 7.4.6 Port Pins 7.5 Register Description 7.5.1 MCUCR – MCU Control Register 7.5.2 PRR – Power Reduction Register 8. System Control and Reset 8.1 Resetting the AVR 8.2 Reset Sources 8.2.1 Power-on Reset 8.2.2 External Reset 8.2.3 Brown-out Detection 8.2.4 Watchdog Reset 8.3 Internal Voltage Reference 8.3.1 Voltage Reference Enable Signals and Start-up Time 8.4 Watchdog Timer 8.4.1 Timed Sequences for Changing the Configuration of the Watchdog Timer 8.4.2 Code Example 8.5 Register Description 8.5.1 MCUSR – MCU Status Register 8.5.2 WDTCSR – Watchdog Timer Control and Status Register 9. Interrupts 9.1 Interrupt Vectors 9.2 External Interrupts 9.2.1 Low Level Interrupt 9.2.2 Pin Change Interrupt Timing 9.3 Register Description 9.3.1 MCUCR – MCU Control Register 9.3.2 GIMSK – General Interrupt Mask Register 9.3.3 GIFR – General Interrupt Flag Register 9.3.4 PCMSK1 – Pin Change Mask Register 1 9.3.5 PCMSK0 – Pin Change Mask Register 0 10. I/O Ports 10.1 Ports as General Digital I/O 10.1.1 Configuring the Pin 10.1.2 Toggling the Pin 10.1.3 Switching Between Input and Output 10.1.4 Reading the Pin Value 10.1.5 Digital Input Enable and Sleep Modes 10.1.6 Unconnected Pins 10.1.7 Program Examples 10.2 Alternate Port Functions 10.2.1 Alternate Functions of Port A 10.2.2 Alternate Functions of Port B 10.3 Register Description 10.3.1 MCUCR – MCU Control Register 10.3.2 PORTA – Port A Data Register 10.3.3 DDRA – Port A Data Direction Register 10.3.4 PINA – Port A Input Pins 10.3.5 PORTB – Port B Data Register 10.3.6 DDRB – Port B Data Direction Register 10.3.7 PINB – Port B Input Pins 11. 8-bit Timer/Counter0 with PWM 11.1 Features 11.2 Overview 11.2.1 Registers 11.2.2 Definitions 11.3 Clock Sources 11.4 Counter Unit 11.5 Output Compare Unit 11.5.1 Force Output Compare 11.5.2 Compare Match Blocking by TCNT0 Write 11.5.3 Using the Output Compare Unit 11.6 Compare Match Output Unit 11.6.1 Compare Output Mode and Waveform Generation 11.7 Modes of Operation 11.7.1 Normal Mode 11.7.2 Clear Timer on Compare Match (CTC) Mode 11.7.3 Fast PWM Mode 11.7.4 Phase Correct PWM Mode 11.8 Timer/Counter Timing Diagrams 11.9 Register Description 11.9.1 TCCR0A – Timer/Counter Control Register A 11.9.2 TCCR0B – Timer/Counter Control Register B 11.9.3 TCNT0 – Timer/Counter Register 11.9.4 OCR0A – Output Compare Register A 11.9.5 OCR0B – Output Compare Register B 11.9.6 TIMSK0 – Timer/Counter 0 Interrupt Mask Register 11.9.7 TIFR0 – Timer/Counter 0 Interrupt Flag Register 12. 16-bit Timer/Counter1 12.1 Features 12.2 Overview 12.2.1 Registers 12.2.2 Definitions 12.2.3 Compatibility 12.3 Timer/Counter Clock Sources 12.4 Counter Unit 12.5 Input Capture Unit 12.5.1 Input Capture Trigger Source 12.5.2 Noise Canceler 12.5.3 Using the Input Capture Unit 12.6 Output Compare Units 12.6.1 Force Output Compare 12.6.2 Compare Match Blocking by TCNT1 Write 12.6.3 Using the Output Compare Unit 12.7 Compare Match Output Unit 12.7.1 Compare Output Mode and Waveform Generation 12.8 Modes of Operation 12.8.1 Normal Mode 12.8.2 Clear Timer on Compare Match (CTC) Mode 12.8.3 Fast PWM Mode 12.8.4 Phase Correct PWM Mode 12.8.5 Phase and Frequency Correct PWM Mode 12.9 Timer/Counter Timing Diagrams 12.10 Accessing 16-bit Registers 12.10.1 Reusing the Temporary High Byte Register 12.11 Register Description 12.11.1 TCCR1A – Timer/Counter1 Control Register A 12.11.2 TCCR1B – Timer/Counter1 Control Register B 12.11.3 TCCR1C – Timer/Counter1 Control Register C 12.11.4 TCNT1H and TCNT1L – Timer/Counter1 12.11.5 OCR1AH and OCR1AL – Output Compare Register 1 A 12.11.6 OCR1BH and OCR1BL – Output Compare Register 1 B 12.11.7 ICR1H and ICR1L – Input Capture Register 1 12.11.8 TIMSK1 – Timer/Counter Interrupt Mask Register 1 12.11.9 TIFR1 – Timer/Counter Interrupt Flag Register 1 13. Timer/Counter Prescaler 13.1 Prescaler Reset 13.2 External Clock Source 13.3 Register Description 13.3.1 GTCCR – General Timer/Counter Control Register 14. USI – Universal Serial Interface 14.1 Features 14.2 Overview 14.3 Functional Descriptions 14.3.1 Three-wire Mode 14.3.2 SPI Master Operation Example 14.3.3 SPI Slave Operation Example 14.3.4 Two-wire Mode 14.3.5 Start Condition Detector 14.3.6 Clock speed considerations 14.4 Alternative USI Usage 14.4.1 Half-Duplex Asynchronous Data Transfer 14.4.2 4-Bit Counter 14.4.3 12-Bit Timer/Counter 14.4.4 Edge Triggered External Interrupt 14.4.5 Software Interrupt 14.5 Register Descriptions 14.5.1 USICR – USI Control Register 14.5.2 USISR – USI Status Register 14.5.3 USIDR – USI Data Register 14.5.4 USIBR – USI Buffer Register 15. Analog Comparator 15.1 Analog Comparator Multiplexed Input 15.2 Register Description 15.2.1 ACSR – Analog Comparator Control and Status Register 15.2.2 ADCSRB – ADC Control and Status Register B 15.2.3 DIDR0 – Digital Input Disable Register 0 16. Analog to Digital Converter 16.1 Features 16.2 Overview 16.3 Operation 16.4 Starting a Conversion 16.5 Prescaling and Conversion Timing 16.6 Changing Channel or Reference Selection 16.6.1 ADC Input Channels 16.6.2 ADC Voltage Reference 16.7 ADC Noise Canceler 16.8 Analog Input Circuitry 16.9 Noise Canceling Techniques 16.10 ADC Accuracy Definitions 16.11 ADC Conversion Result 16.11.1 Single Ended Conversion 16.11.2 Unipolar Differential Conversion 16.11.3 Bipolar Differential Conversion 16.12 Temperature Measurement 16.13 Register Description 16.13.1 ADMUX – ADC Multiplexer Selection Register 16.13.2 ADCSRA – ADC Control and Status Register A 16.13.3 ADCL and ADCH – ADC Data Register 16.13.3.1 ADLAR = 0 16.13.3.2 ADLAR = 1 16.13.4 ADCSRB – ADC Control and Status Register B 16.13.5 DIDR0 – Digital Input Disable Register 0 17. debugWIRE On-chip Debug System 17.1 Features 17.2 Overview 17.3 Physical Interface 17.4 Software Break Points 17.5 Limitations of debugWIRE 17.6 Register Description 17.6.1 DWDR – debugWire Data Register 18. Self-Programming the Flash 18.1 Performing Page Erase by SPM 18.2 Filling the Temporary Buffer (Page Loading) 18.3 Performing a Page Write 18.4 Addressing the Flash During Self-Programming 18.5 EEPROM Write Prevents Writing to SPMCSR 18.6 Reading Lock, Fuse and Signature Data from Software 18.6.1 Reading Lock Bits from Firmware 18.6.2 Reading Fuse Bits from Firmware 18.6.3 Reading Device Signature Imprint Table from Firmware 18.7 Preventing Flash Corruption 18.8 Programming Time for Flash when Using SPM 18.9 Register Description 18.9.1 SPMCSR – Store Program Memory Control and Status Register 19. Memory Programming 19.1 Program And Data Memory Lock Bits 19.2 Fuse Bytes 19.2.1 Latching of Fuses 19.3 Device Signature Imprint Table 19.3.1 Signature Bytes 19.3.2 Calibration Byte 19.4 Page Size 19.5 Serial Programming 19.5.1 Serial Programming Algorithm 19.5.2 Serial Programming Instruction set 19.6 High-voltage Serial Programming 19.7 High-Voltage Serial Programming Algorithm 19.7.1 Enter High-voltage Serial Programming Mode 19.7.2 Considerations for Efficient Programming 19.7.3 Chip Erase 19.7.4 Programming the Flash 19.7.5 Programming the EEPROM 19.7.6 Reading the Flash 19.7.7 Reading the EEPROM 19.7.8 Programming and Reading the Fuse and Lock Bits 19.7.9 Reading the Signature Bytes and Calibration Byte 19.7.10 Power-off sequence 20. Electrical Characteristics 20.1 Absolute Maximum Ratings* 20.2 DC Characteristics 20.3 Speed 20.4 Clock Characteristics 20.4.1 Accuracy of Calibrated Internal Oscillator 20.4.2 External Clock Drive 20.5 System and Reset Characteristics 20.5.1 Power-On Reset 20.5.2 Brown-Out Detection 20.6 ADC Characteristics 20.7 Analog Comparator Characteristics 20.8 Serial Programming Characteristics 20.9 High-Voltage Serial Programming Characteristics 21. Typical Characteristics 21.1 Supply Current of I/O Modules 21.1.1 Example 21.2 ATtiny24A 21.2.1 Current Consumption in Active Mode 21.2.2 Current Consumption in Idle Mode 21.2.3 Current Consumption in Power-down Mode 21.2.4 Current Consumption in Reset 21.2.5 Current Consumption of Peripheral Units 21.2.6 Pull-up Resistors 21.2.7 Output Driver Strength 21.2.8 Input Threshold and Hysteresis (for I/O Ports) 21.2.9 BOD, Bandgap and Reset 21.2.10 Analog Comparator Offset 21.2.11 Internal Oscillator Speed 21.3 ATtiny44A 21.3.1 Current Consumption in Active Mode 21.3.2 Current Consumption in Idle Mode 21.3.3 Standby Supply Current 21.3.4 Current Consumption in Power-down Mode 21.3.5 Current Consumption in Reset 21.3.6 Current Consumption of Peripheral Units 21.3.7 Pull-up Resistors 21.3.8 Output Driver Strength 21.3.9 Input Threshold and Hysteresis (for I/O Ports) 21.3.10 BOD, Bandgap and Reset 21.3.11 Analog Comparator Offset 21.3.12 Internal Oscillator Speed 21.4 ATtiny84A 21.4.1 Current Consumption in Active Mode 21.4.2 Current Consumption in Idle Mode 21.4.3 Current Consumption in Power-down Mode 21.4.4 Current Consumption in Reset 21.4.5 Current Consumption of Peripheral Units 21.4.6 Pull-up Resistors 21.4.7 Output Driver Strength 21.4.8 Input Threshold and Hysteresis (for I/O Ports) 21.4.9 BOD, Bandgap and Reset 21.4.10 Analog Comparator Offset 21.4.11 Internal Oscillator Speed 22. Register Summary 23. Instruction Set Summary 24. Ordering Information 24.1 ATtiny24A 24.2 ATtiny44A 24.3 ATtiny84A 25. Packaging Information 25.1 14S1 25.2 14P3 25.3 15CC1 25.4 20M1 25.5 20M2 26. Errata 26.1 ATtiny24A 26.1.1 Rev. H 26.1.2 Rev. G 26.1.3 Rev. F 26.2 ATtiny44A 26.2.1 Rev. G 26.2.2 Rev. F 26.2.3 Rev. E 26.3 ATtiny84A 26.3.1 Rev. C 27. Datasheet Revision History 27.1 Rev. 8183F – 06/12 27.2 Rev. 8183E – 01/12 27.3 Rev. 8183D – 04/11 27.4 Rev. 8183C – 03/11 27.5 Rev. 8183B – 03/10 27.6 Rev. 8183A – 12/08 Table of Contents