Datasheet MCP6V01, MCP6V02, MCP6V03 (Microchip) - 4

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MCP6V01/2/3 TABLE 1-1: DC ELECTRICAL SPECIFICATIONS (CONTINUED) Electrical Characteristics:
Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 20 kΩ to VL, and CS = GND (refer to Figure 1-5 and Figure 1-6).
Parameters Sym Min Typ Max Units Conditions Output
Maximum Output Voltage Swing VOL, VOH VSS + 15 — VDD − 15 mV G = +2, 0.5V input overdrive Output Short Circuit Current ISC — ±7 — mA VDD = 1.8V ISC — ±22 — mA VDD = 5.5V
Power Supply
Supply Voltage VDD 1.8 — 5.5 V Quiescent Current per amplifier IQ 200 300 400 µA IO = 0 POR Trip Voltage VPOR 1.15 — 1.65 V
Note 1:
Set by design and characterization. Due to thermal junction and other effects in the production environment, these parts can only be screened in production (except TC1; see
Appendix B: “Offset Related Test Screens”
).
2:
Figure 2-18 shows how VCMR changed across temperature for the first three production lots.
TABLE 1-2: AC ELECTRICAL SPECIFICATIONS Electrical Characteristics:
Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 20 kΩ to VL, CL = 60 pF, and CS = GND (refer to Figure 1-5 and Figure 1-6).
Parameters Sym Min Typ Max Units Conditions Amplifier AC Response
Gain Bandwidth Product GBWP — 1.3 — MHz Slew Rate SR — 0.5 — V/µs Phase Margin PM — 65 — ° G = +1
Amplifier Noise Response
Input Noise Voltage Eni — 0.79 — µVP-P f = 0.01 Hz to 1 Hz Eni — 2.5 — µVP-P f = 0.1 Hz to 10 Hz Input Noise Voltage Density eni — 120 — nV/√Hz f < 2.5 kHz eni — 45 — nV/√Hz f = 100 kHz Input Noise Current Density ini — 0.6 — fA/√Hz
Amplifier Distortion (Note 1)
Intermodulation Distortion (AC) IMD — <1 — µVPK VCM tone = 50 mVPK at 1 kHz, GN = 1, VDD = 1.8V IMD — <1 — µVPK VCM tone = 50 mVPK at 1 kHz, GN = 1, VDD = 5.5V
Amplifier Step Response
Start Up Time tSTR — 500 — µs VOS within 50 µV of its final value Offset Correction Settling Time tSTL — 300 — µs G = +1, VIN step of 2V, VOS within 50 µV of its final value Output Overdrive Recovery Time tODR — 100 — µs G = -100, ±0.5V input overdrive to VDD/2, VIN 50% point to VOUT 90% point
(Note 2) Note 1:
These parameters were characterized using the circuit in Figure 1-7. Figure 2-37 and Figure 2-38 show both an IMD tone at DC and a residual tone at1 kHz; all other IMD and clock tones are spread by the randomization circuitry.
2:
tODR includes some uncertainty due to clock edge timing. DS22058C-page 4 © 2008 Microchip Technology Inc. Document Outline 1.0 Electrical Characteristics 1.1 Absolute Maximum Ratings † 1.2 Specifications TABLE 1-1: DC Electrical Specifications TABLE 1-2: AC Electrical Specifications TABLE 1-3: Digital Electrical Specifications TABLE 1-4: Temperature Specifications 1.3 Timing Diagrams FIGURE 1-1: Amplifier Start Up. FIGURE 1-2: Offset Correction Settling Time. FIGURE 1-3: Output Overdrive Recovery. FIGURE 1-4: Chip Select (MCP6V03). 1.4 Test Circuits FIGURE 1-5: AC and DC Test Circuit for Most Non-Inverting Gain Conditions. FIGURE 1-6: AC and DC Test Circuit for Most Inverting Gain Conditions. FIGURE 1-7: Test Circuit for Dynamic Input Behavior. 2.0 Typical Performance Curves 2.1 DC Input Precision FIGURE 2-1: Input Offset Voltage. FIGURE 2-2: Input Offset Voltage Drift. FIGURE 2-3: Input Offset Voltage Quadratic Temp Co. FIGURE 2-4: Input Offset Voltage vs. Power Supply Voltage with VCM = VCMR_L. FIGURE 2-5: Input Offset Voltage vs. Power Supply Voltage with VCM = VCMR_H. FIGURE 2-6: Input Offset Voltage vs. Output Voltage. FIGURE 2-7: Input Offset Voltage vs. Common Mode Voltage with VDD = 1.8V. FIGURE 2-8: Input Offset Voltage vs. Common Mode Voltage with VDD = 5.5V. FIGURE 2-9: CMRR. FIGURE 2-10: PSRR. FIGURE 2-11: DC Open-Loop Gain. FIGURE 2-12: CMRR and PSRR vs. Ambient Temperature. FIGURE 2-13: DC Open-Loop Gain vs. Ambient Temperature. FIGURE 2-14: Input Bias and Offset Currents vs. Common Mode Input Voltage with TA = +85˚C. FIGURE 2-15: Input Bias and Offset Currents vs. Common Mode Input Voltage with TA = +125˚C. FIGURE 2-16: Input Bias and Offset Currents vs. Ambient Temperature with VDD = +5.5V. FIGURE 2-17: Input Bias Current vs. Input Voltage (below VSS). 2.2 Other DC Voltages and Currents FIGURE 2-18: Input Common Mode Voltage Headroom (Range) vs. Ambient Temperature. FIGURE 2-19: Output Voltage Headroom vs. Output Current. FIGURE 2-20: Output Voltage Headroom vs. Ambient Temperature. FIGURE 2-21: Output Short Circuit Current vs. Power Supply Voltage. FIGURE 2-22: Supply Current vs. Power Supply Voltage. FIGURE 2-23: Power On Reset Trip Voltage. FIGURE 2-24: Power On Reset Voltage vs. Ambient Temperature. 2.3 Frequency Response FIGURE 2-25: CMRR and PSRR vs. Frequency. FIGURE 2-26: Open-Loop Gain vs. Frequency with VDD = 1.8V. FIGURE 2-27: Open-Loop Gain vs. Frequency with VDD = 5.5V. FIGURE 2-28: Gain Bandwidth Product and Phase Margin vs. Ambient Temperature. FIGURE 2-29: Gain Bandwidth Product and Phase Margin vs. Common Mode Input Voltage. FIGURE 2-30: Gain Bandwidth Product and Phase Margin vs. Output Voltage. FIGURE 2-31: Closed-Loop Output Impedance vs. Frequency with VDD = 1.8V. FIGURE 2-32: Closed-Loop Output Impedance vs. Frequency with VDD = 5.5V. FIGURE 2-33: Channel-to-Channel Separation vs. Frequency. FIGURE 2-34: Maximum Output Voltage Swing vs. Frequency. 2.4 Input Noise and Distortion FIGURE 2-35: Input Noise Voltage Density vs. Frequency. FIGURE 2-36: Input Noise Voltage Density vs. Input Common Mode Voltage. FIGURE 2-37: Inter-Modulation Distortion vs. Frequency with VCM Disturbance (see Figure 1-7). FIGURE 2-38: Inter-Modulation Distortion vs. Frequency with VDD Disturbance (see Figure 1-7). FIGURE 2-39: Input Noise vs. Time with 1 Hz and 10 Hz Filters and VDD =1.8V. FIGURE 2-40: Input Noise vs. Time with 1 Hz and 10 Hz Filters and VDD =5.5V. 2.5 Time Response FIGURE 2-41: Input Offset Voltage vs. Time with Temperature Change. FIGURE 2-42: Input Offset Voltage vs. Time at Power Up. FIGURE 2-43: The MCP6V01/2/3 family shows no input phase reversal with overdrive. FIGURE 2-44: Non-inverting Small Signal Step Response. FIGURE 2-45: Non-inverting Large Signal Step Response. FIGURE 2-46: Inverting Small Signal Step Response. FIGURE 2-47: Inverting Large Signal Step Response. FIGURE 2-48: Slew Rate vs. Ambient Temperature. FIGURE 2-49: Output Overdrive Recovery vs. Time with G = -100 V/V. FIGURE 2-50: Output Overdrive Recovery Time vs. Inverting Gain. 2.6 Chip Select Response (MCP6V03 only) FIGURE 2-51: Chip Select Current vs. Power Supply Voltage. FIGURE 2-52: Power Supply Current vs. Chip Select Voltage with VDD = 1.8V. FIGURE 2-53: Power Supply Current vs. Chip Select Voltage with VDD = 5.5V. FIGURE 2-54: Chip Select Current vs. Chip Select Voltage. FIGURE 2-55: Chip Select Voltage, Output Voltage vs. Time with VDD = 1.8V. FIGURE 2-56: Chip Select Voltage, Output Voltage vs. Time with VDD = 5.5V. FIGURE 2-57: Chip Select Relative Logic Thresholds vs. Ambient Temperature. FIGURE 2-58: Chip Select Hysteresis. FIGURE 2-59: Chip Select Turn On Time vs. Ambient Temperature. FIGURE 2-60: Chip Select’s Pull-down Resistor (RPD) vs. Ambient Temperature. FIGURE 2-61: Quiescent Current in Shutdown vs. Power Supply Voltage. 3.0 Pin Descriptions TABLE 3-1: Pin Function Table 3.1 Analog Outputs 3.2 Analog Inputs 3.3 Power Supply Pins 3.4 Chip Select (CS) Digital Input 3.5 Exposed Thermal Pad (EP) 4.0 Applications 4.1 Overview of Auto-zeroing Operation FIGURE 4-1: Simplified Auto-zeroed Op Amp Functional Diagram. FIGURE 4-2: Normal Mode of Operation (f1); Equivalent Amplifier Diagram. FIGURE 4-3: Auto-zeroing Mode of Operation (f2); Equivalent Diagram. 4.2 Other Functional Blocks FIGURE 4-4: Simplified Analog Input ESD Structures. FIGURE 4-5: Protecting the Analog Inputs. 4.3 Application Tips FIGURE 4-6: Output Resistor, RISO, Stabilizes Capacitive Loads. FIGURE 4-7: Recommended RISO values for Capacitive Loads. FIGURE 4-8: Output Load Issue. FIGURE 4-9: One Solution To Output Load Issue. FIGURE 4-10: Additional Supply Filtering. FIGURE 4-11: PCB Layout and Schematic for Single Non-inverting and Inverting Amplifiers. FIGURE 4-12: PCB Layout and Schematic for Single Difference Amplifier. FIGURE 4-13: PCB Layout and Schematic for Dual Non-inverting Amplifier. FIGURE 4-14: PCB Layout for Individual Resistors. 4.4 Typical Applications FIGURE 4-15: Simple Design. FIGURE 4-16: High Performance Design. FIGURE 4-17: RTD Sensor. FIGURE 4-18: Thermocouple Sensor; Simplified Circuit. FIGURE 4-19: Thermocouple Sensor. FIGURE 4-20: Offset Correction. FIGURE 4-21: Precision Comparator. 5.0 Design Aids 5.1 SPICE Macro Model 5.2 FilterLab® Software 5.3 Mindi™ Circuit Designer & Simulator 5.4 Microchip Advanced Part Selector (MAPS) 5.5 Analog Demonstration and Evaluation Boards 5.6 Application Notes 6.0 Packaging Information 6.1 Package Marking Information