Datasheet MCP6031, MCP6032, MCP6035, MCP6034 (Microchip) - 4

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MCP6031/2/3/4 MCP6033 CHIP SELECT ELECTRICAL CHARACTERISTICS Electrical Specifications:
Unless otherwise indicated, VDD = +1.8V to +5.5V, VSS =GND, TA = +25°C, VCM = VDD/2, VOUT = VDD/2, VL = VDD/2, CL = 60 pF, RL = 1 MΩ to VL and CS is tied low (Refer to Figure 1-1).
Parameters Sym Min Typ Max Units Conditions CS Low Specifications
CS Logic Threshold, Low VIL VSS — 0.2VDD V CS Input Current, Low ICSL — -10 — pA CS = VSS
CS High Specifications
CS Logic Threshold, High VIH 0.8VDD VDD V CS Input Current, High ICSH — 10 — pA CS = VDD GND Current ISS — -400 — pA CS = VDD Amplifier Output Leakage IO(LEAK) — 10 — pA CS = VDD
CS Dynamic Specifications
CS Low to Amplifier Output tON — 4 100 ms CS ≤ 0.2VDD to VOUT = 0.9VDD/2, Turn-on Time G = +1 V/V, VIN = VDD/2, RL = 50 kΩ to VL = VSS. CS High to Amplifier Output tOFF — 10 — µs CS ≥ 0.8VDD to VOUT = 0.1VDD/2, High-Z G = +1 V/V, VIN = VDD/2, RL = 50 kΩ to VL = VSS. CS Hysteresis VHYST — 0.3VDD — V CS VIL VIH tON tOFF VOUT High-Z High-Z -0.9 µA -400 pA (typical) I -400 pA SS (typical) (typical) ICS 10 pA (typical)
FIGURE 1-1:
Timing Diagram for the CS Pin on the MCP6033. DS22041B-page 4 © 2008 Microchip Technology Inc. Document Outline 1.0 Electrical Characteristics FIGURE 1-1: Timing Diagram for the CS Pin on the MCP6033. 1.1 Test Circuits FIGURE 1-2: AC and DC Test Circuit for Most Non-Inverting Gain Conditions. FIGURE 1-3: AC and DC Test Circuit for Most Inverting Gain Conditions. 2.0 Typical Performance Curves FIGURE 2-1: Input Offset Voltage with VDD = 3.0V. FIGURE 2-2: Input Offset Voltage Drift with VDD = 3.0V and TA £ +85˚C. FIGURE 2-3: Input Offset Voltage Drift with VDD = 3.0V and TA ³ +85˚C. FIGURE 2-4: Input Offset Voltage vs. Common Mode Input Voltage with VDD = 5.5V. FIGURE 2-5: Input Offset Voltage vs. Common Mode Input Voltage with VDD = 1.8V. FIGURE 2-6: Input Offset Voltage vs. Output Voltage. FIGURE 2-7: Input Noise Voltage Density vs. Frequency. FIGURE 2-8: Input Noise Voltage Density vs. Common Mode Input Voltage. FIGURE 2-9: Common Mode Rejection Ratio, Power Supply Rejection Ratio vs. Frequency. FIGURE 2-10: Common Mode Rejection Ratio, Power Supply Rejection Ratio vs. Ambient Temperature. FIGURE 2-11: Input Bias, Offset Currents vs. Ambient Temperature. FIGURE 2-12: Input Bias Current vs. Common Mode Input Voltage. FIGURE 2-13: Quiescent Current vs Ambient Temperature. FIGURE 2-14: Quiescent Current vs. Power Supply Voltage with VCM = VDD. FIGURE 2-15: Quiescent Current vs. Power Supply Voltage with VCM = VSS. FIGURE 2-16: Open-Loop Gain, Phase vs. Frequency. FIGURE 2-17: DC Open-Loop Gain vs. Power Supply Voltage. FIGURE 2-18: DC Open-Loop Gain vs. Output Voltage Headroom. FIGURE 2-19: Channel-to-Channel Separation vs. Frequency ( MCP6032/4 only). FIGURE 2-20: Gain Bandwidth Product, Phase Margin vs. Common Mode Input Voltage. FIGURE 2-21: Gain Bandwidth Product, Phase Margin vs. Ambient Temperature. FIGURE 2-22: Gain Bandwidth Product, Phase Margin vs. Ambient Temperature. FIGURE 2-23: Ouput Short Circuit Current vs. Power Supply Voltage. FIGURE 2-24: Output Voltage Swing vs. Frequency. FIGURE 2-25: Output Voltage Headroom vs. Output Current. FIGURE 2-26: Output Voltage Headroom vs. Ambient Temperature. FIGURE 2-27: Slew Rate vs. Ambient Temperature. FIGURE 2-28: Small Signal Non-Inverting Pulse Response. FIGURE 2-29: Small Signal Inverting Pulse Response. FIGURE 2-30: Large Signal Non-Inverting Pulse Response. FIGURE 2-31: Large Signal Inverting Pulse Response. FIGURE 2-32: The MCP6031/2/3/4 family shows no phase reversal . FIGURE 2-33: Chip Select (CS) to Amplifier Output Response Time (MCP6033 only). FIGURE 2-34: Chip Select (CS) Hysteresis (MCP6033 only) with VDD = 5.5V. FIGURE 2-35: Chip Select (CS) Hysteresis (MCP6033 only) with VDD = 3.0V. FIGURE 2-36: Chip Select (CS) Hysteresis (MCP6033 only) with VDD = 1.8V. FIGURE 2-37: Closed Loop Output Impedance vs. Frequency. FIGURE 2-38: Measured Input Current vs. Input Voltage (below VSS). 3.0 Pin Descriptions TABLE 3-1: Pin Function Table 3.1 Analog Outputs 3.2 Analog Inputs 3.3 Chip Select Digital Input 3.4 Power Supply Pins 4.0 Application Information 4.1 Rail-to-Rail Input FIGURE 4-1: Simplified Analog Input ESD Structures. FIGURE 4-2: Protecting the Analog Inputs. 4.2 Rail-to-Rail Output 4.3 Output Loads and Battery Life 4.4 Capacitive Loads FIGURE 4-3: Output resistor, RISO stabilizes large capacitive loads. FIGURE 4-4: Recommended RISO values for Capacitive Loads. 4.5 MCP6033 Chip Select 4.6 Supply Bypass 4.7 Unused Op Amps FIGURE 4-5: Unused Op Amps. 4.8 PCB Surface Leakage FIGURE 4-6: Example Guard Ring Layout for Inverting Gain. 4.9 Application Circuits FIGURE 4-7: High Side Battery Current Sensor. FIGURE 4-8: Precision, Non-inverting Comparator. FIGURE 4-9: Driving the MCP3421 using an R-C Snubber. 5.0 Design Aids 5.1 SPICE Macro Model 5.2 FilterLab® Software 5.3 Mindi™ Circuit Designer & Simulator 5.4 MAPS (Microchip Advanced Part Selector) 5.5 Analog Demonstration and Evaluation Boards 5.6 Application Notes 6.0 Packaging Information 6.1 Package Marking Information