Datasheet LTC4417 (Linear Technology) - 10

LTC4417
operaTion
The Functional Block Diagram displays the main functional by the reverse current blocking threshold of 120mV. The blocks of this device. The LTC4417 connects one of three output of the REV comparator is latched, resetting when power supplies to a common output, VOUT, based on user its respective channel is turned off. defined priority. Connection is made by enhancing external The LTC4417 gate driver pulls down on G1, G2 and back-to-back P-channel MOSFETs. Unlike a diode-OR, G3 with a strong P-channel source follower and a 2µA which always passes the highest supply voltage to the current source. When the clamp voltage is reached, the output, the LTC4417 lets one use a lower voltage supply P-channel source follower is back biased, leaving the for primary power and a higher voltage supply as second- 2µA current source to hold G1, G2 and G3 at the clamp ary or backup power. voltage. To minimize inrush current at start-up, the gate During normal operation the LTC4417 continuously moni- driver soft-starts the first input supply to connect VOUT, tors V1, V2 and V3 through its respective OV1, OV2 and OV3 at a rate of around 5V/ms terminating when any channel and UV1, UV2 and UV3 pins using precision overvoltage disconnects or 32ms has elapsed. Once slew rate control and undervoltage comparators. The highest priority input has terminated, the gate driver quickly turns on and off supply whose voltage is within its respective OV/UV window external back-to-back P-channel MOSFETs as needed. A for at least 256ms is considered valid and is connected to SHDN low to high transition or VOUT drooping below 0.7V VOUT through external back-to-back P-channel MOSFETs. reactivates soft-start. VALID1, VALID2 and VALID3 pull low to indicate when the When EN is driven above 1V the highest valid priority V1, V2 and V3 input supplies are valid. input supply is connected to VOUT. The high voltage EN Hysteresis on the OV and UV threshold is adjustable. comparator disconnects all channels when EN is driven Connecting a resistor, RHYS, between HYS and ground below 1V. The LTC4417 continues to monitor the OV and forces 63mV/RHYS current to flow out of OV1, OV2 and UV pins and reflects the current input supply status with OV3 and into UV1, UV2 and UV3 to create hysteresis when VALID1, VALID2 and VALID3. When four or more sup- outside their respective OV/UV windows. Connecting HYS plies need to be prioritized, connect the higher priority to ground sets the OV and UV comparator hysteresis to LTC4417’s CAS to the lower priority LTC4417’s EN. If 30mV. See the Application Information for more details. VOUT is allowed to fall below 0.7V, the next connecting During channel transitions, monitoring circuitry prevents input supply is soft-started. cross conduction between input channels and reverse con- The high voltage SHDN comparator forces the LTC4417 into duction from VOUT using a break-before-make architecture. a low current state when SHDN is forced below 0.8V. While The VGS comparator monitors the disconnecting channel’s in the low current state, all channels are disconnected, OV gate pin voltage (G1, G2 or G3). When the gate voltage is and UV comparators are disabled, and all 256ms timers 350mV from its common source connection (VS1, VS2 or are reset. When SHDN transitions from low to high, the VS3), the VGS comparator latches the output to indicate first validated input to connect to VOUT is soft-started. the channel is off and allows the next valid priority input Two separate internal power rails ensure the LTC4417 is supply to connect to VOUT, preventing cross conduction functional when one or more input supply is present and between channels. The latch is reset when the channel is above 2.3V. V turned on. BESTGEN generates a VBLDO rail from the highest V1, V2 and V3 and VOUT voltage. VBLDO powers To prevent reverse conduction from VOUT to V1, V2 and V3 the UVLO, bandgap, and VOUT comparator. The internal during channel switchover, the REV comparator monitors VLDO powers all other circuits from VOUT provided VOUT is the connecting input supply (V1, V2 or V3) and output greater than 2.4V. If VOUT is less than 2.3V, VLDO powers voltage (VOUT). The REV comparator delays the connection all other circuits from the highest priority supply available. until the output voltage droops lower than the input voltage If all sources are invalid or the LTC4417 is shut down, VLDO connects to VBLDO. 4417f 10 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Functional Block Diagram Timing Diagram Operation Applications Information Typical Applications Package Description Typical Application Related Parts