Datasheet LTC2323-12 (Analog Devices) - 5
| Hersteller | Analog Devices |
| Beschreibung | Dual, 12-Bit + Sign, 5Msps Differential Input ADC with Wide Input Common Mode Range |
| Seiten / Seite | 26 / 5 — ADC TIMING CHARACTERISTICS. The. denotes the specifications which apply … |
| Dateiformat / Größe | PDF / 1.2 Mb |
| Dokumentensprache | Englisch |
ADC TIMING CHARACTERISTICS. The. denotes the specifications which apply over the full operating
Modelllinie für dieses Datenblatt
Textversion des Dokuments
LTC2323-12
ADC TIMING CHARACTERISTICS The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C (Note 4). SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fSMPL Maximum Sampling Frequency l 5 Msps tCYC Time Between Conversions (Note 11) l 200 1000000 ns tCONV Conversion Time l 161.9 ns tCNVH CNV High Time l 35 ns tDCNVSCKL SCK Quiet Time from CNV↓ (Note 11) l 10 ns tDSCKLCNVH SCK Delay Time to CNV↑ (Note 11) l 20 ns tSCK SCK Period (Notes 12, 13) l 9.4 ns tSCKH SCK High Time l 4 ns tSCKL SCK Low Time l 4 ns tDSCKCLKOUT SCK to CLKOUT Delay (Note 12) l 2.5 ns tDCLKOUTSDOV SDO Data Valid Delay from CLKOUT↓ CL = 5pF (Note 12) l 2 ns tHSDO SDO Data Remains Valid Delay from CL = 5pF (Note 11) l 2 ns CLKOUT↓ tDCNVSDOV SDO Data Valid Delay from CNV↓ CL = 5pF (Note 11) l 2.5 3 ns tDCNVSDOZ Bus Relinquish Time After CNV↑ (Note 11) l 3 ns tWAKE REFOUT1,2 Wakeup Time CREFOUT1,2 = 10μF 10 ms
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
Note 8:
All specifications in dB are referred to a full-scale ±4.096V input may cause permanent damage to the device. Exposure to any Absolute with REFIN = 4.096V. Maximum Rating condition for extended periods may affect device
Note 9:
When REFOUT1,2 is overdriven, the internal reference buffer must reliability and lifetime. be turned off by setting REFINT = 0V.
Note 2:
All voltage values are with respect to ground.
Note 10:
fSMPL = 5MHz, IREFBUF varies proportionally with sample rate.
Note 3:
When these pin voltages are taken below ground, or above VDD
Note 11:
Guaranteed by design, not subject to test. or OVDD, they will be clamped by internal diodes. This product can handle
Note 12:
Parameter tested and guaranteed at OV input currents up to 100mA below ground, or above V DD = 1.71V and DD or OVDD, without OV latch-up. DD = 2.5V.
Note 13:
t
Note 4
: V SCK of 9.4ns maximum allows a shift clock frequency up to DD = 5V, OVDD = 2.5V, REFOUT1,2 = 4.096V, fSMPL = 5MHz. 105MHz for rising edge capture.
Note 5:
Recommended operating conditions.
Note 14:
Temperature coefficient is calculated by dividing the maximum
Note 6:
Integral nonlinearity is defined as the deviation of a code from a change in output voltage by the specified temperature range. straight line passing through the actual endpoints of the transfer curve.
Note 15:
CNV is driven from a low jitter digital source, typically at OV The deviation is measured from the center of the quantization band. DD logic levels. This input pin has a TTL style input that will draw a small
Note 7:
Bipolar zero error is the offset voltage measured from –0.5LSB amount of current. when the output code flickers between 0 0000 0000 0000 and 1 1111
Note 16:
1LSB = 2 • REFOUT1,2/212 1111 1111. Full-scale bipolar error is the worst-case of –FS or +FS un-trimmed deviation from ideal first and last code transitions and includes the effect of offset error. 0.8 • OVDD tWIDTH 0.2 • OVDD t tDELAY 50% 50% DELAY 232312 F01 0.8 • OVDD 0.8 • OVDD 0.2 • OVDD 0.2 • OVDD
Figure 1. Voltage Levels for Timing Specifications
232312fb For more information www.linear.com/LTC2323-12 5 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Electrical Characteristics Pin Configuration Converter Characteristics Dynamic Accuracy Internal Reference Characteristics Digital Inputs And Digital Outputs Power Requirements ADC Timing Characteristics Typical Performance Characteristics Pin Functions Functional Block Diagram Timing Diagram Applications Information Package Description Revision History Typical Application Related Parts
ADC TIMING CHARACTERISTICS The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C (Note 4). SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fSMPL Maximum Sampling Frequency l 5 Msps tCYC Time Between Conversions (Note 11) l 200 1000000 ns tCONV Conversion Time l 161.9 ns tCNVH CNV High Time l 35 ns tDCNVSCKL SCK Quiet Time from CNV↓ (Note 11) l 10 ns tDSCKLCNVH SCK Delay Time to CNV↑ (Note 11) l 20 ns tSCK SCK Period (Notes 12, 13) l 9.4 ns tSCKH SCK High Time l 4 ns tSCKL SCK Low Time l 4 ns tDSCKCLKOUT SCK to CLKOUT Delay (Note 12) l 2.5 ns tDCLKOUTSDOV SDO Data Valid Delay from CLKOUT↓ CL = 5pF (Note 12) l 2 ns tHSDO SDO Data Remains Valid Delay from CL = 5pF (Note 11) l 2 ns CLKOUT↓ tDCNVSDOV SDO Data Valid Delay from CNV↓ CL = 5pF (Note 11) l 2.5 3 ns tDCNVSDOZ Bus Relinquish Time After CNV↑ (Note 11) l 3 ns tWAKE REFOUT1,2 Wakeup Time CREFOUT1,2 = 10μF 10 ms
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
Note 8:
All specifications in dB are referred to a full-scale ±4.096V input may cause permanent damage to the device. Exposure to any Absolute with REFIN = 4.096V. Maximum Rating condition for extended periods may affect device
Note 9:
When REFOUT1,2 is overdriven, the internal reference buffer must reliability and lifetime. be turned off by setting REFINT = 0V.
Note 2:
All voltage values are with respect to ground.
Note 10:
fSMPL = 5MHz, IREFBUF varies proportionally with sample rate.
Note 3:
When these pin voltages are taken below ground, or above VDD
Note 11:
Guaranteed by design, not subject to test. or OVDD, they will be clamped by internal diodes. This product can handle
Note 12:
Parameter tested and guaranteed at OV input currents up to 100mA below ground, or above V DD = 1.71V and DD or OVDD, without OV latch-up. DD = 2.5V.
Note 13:
t
Note 4
: V SCK of 9.4ns maximum allows a shift clock frequency up to DD = 5V, OVDD = 2.5V, REFOUT1,2 = 4.096V, fSMPL = 5MHz. 105MHz for rising edge capture.
Note 5:
Recommended operating conditions.
Note 14:
Temperature coefficient is calculated by dividing the maximum
Note 6:
Integral nonlinearity is defined as the deviation of a code from a change in output voltage by the specified temperature range. straight line passing through the actual endpoints of the transfer curve.
Note 15:
CNV is driven from a low jitter digital source, typically at OV The deviation is measured from the center of the quantization band. DD logic levels. This input pin has a TTL style input that will draw a small
Note 7:
Bipolar zero error is the offset voltage measured from –0.5LSB amount of current. when the output code flickers between 0 0000 0000 0000 and 1 1111
Note 16:
1LSB = 2 • REFOUT1,2/212 1111 1111. Full-scale bipolar error is the worst-case of –FS or +FS un-trimmed deviation from ideal first and last code transitions and includes the effect of offset error. 0.8 • OVDD tWIDTH 0.2 • OVDD t tDELAY 50% 50% DELAY 232312 F01 0.8 • OVDD 0.8 • OVDD 0.2 • OVDD 0.2 • OVDD
Figure 1. Voltage Levels for Timing Specifications
232312fb For more information www.linear.com/LTC2323-12 5 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Electrical Characteristics Pin Configuration Converter Characteristics Dynamic Accuracy Internal Reference Characteristics Digital Inputs And Digital Outputs Power Requirements ADC Timing Characteristics Typical Performance Characteristics Pin Functions Functional Block Diagram Timing Diagram Applications Information Package Description Revision History Typical Application Related Parts