Datasheet LTC6907 (Analog Devices) - 8
| Hersteller | Analog Devices |
| Beschreibung | Micropower, 40kHz to 4MHz Resistor Set Oscillator in SOT-23 |
| Seiten / Seite | 12 / 8 — APPLICATIO S I FOR ATIO. Selecting R. SET and the Divider Ratio. For any. … |
| Dateiformat / Größe | PDF / 175 Kb |
| Dokumentensprache | Englisch |
APPLICATIO S I FOR ATIO. Selecting R. SET and the Divider Ratio. For any. given frequency, power can be minimized by minimiz-
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LTC6907
U U W U APPLICATIO S I FOR ATIO Selecting R
10000
SET and the Divider Ratio
÷1 ÷3 The LTC6907 contains a master oscillator followed by a ÷10 digital divider (see Block Diagram). RSET determines the 1000 master oscillator frequency and the three level DIV pin sets the divider ratio, N. The range of frequencies accessible in each divider ratio overlap, as shown in Figure 7. This figure is derived from the equations in Table 1.
For any
100
given frequency, power can be minimized by minimiz-
OUTPUT FREQUENCY (kHz)
ing the master oscillator frequency. This implies maxi- mizing R
10
SET and using the lowest possible divider ratio,
10 100 1000
N
. The relationship between RSET, N and the unloaded RSET (kΩ) power consumption is shown in Figure 8. The supply 6907 F07 current decreases for large values of R
Figure 7. R
SET. Refer to the
SET vs Desired Output Frequency
section titled “Jitter and Divide Ratio.” 160 CLOAD = 0
Minimizing Power Consumption
140 ISUPPLY V+ = 3V DIV = –:1 120 TA = 25°C The supply current of the LTC6907 has four current µA) 100 components: 80 • Constant (Independent V+, ƒOUT and CLOAD) 60 • Proportional to ISET (which is the current in RSET) SUPPLY CURRENT ( 40 • Proportional to V+, ƒOUT and CLOAD 20 • Proportional to V+ and R 0 LOAD 10 100 1000 RSET (kΩ) An approximate expression for the total supply current is: 6907 F08 V+
Figure 8. Unloaded Supply Current vs RSET
I+ ≅ 7 A µ + 6 •I + V+ • ƒ • (C + p 5 F)+ SET OUT LOAD 2 • RLOAD
Guarding Against PC Board Leakage
o or, in terms of VSET, The LTC6907 uses relatively large resistance values for V V+ I+ 7 A SET 6 • V+ ≅ µ + + • ƒ • (C + p 5 F R )+ SET to minimize power consumption. For RSET = 500k, R OUT LOAD SET 2 • RLOAD the SET pin current is typically only 13µA. Thus, only 13nA leaking into the SET pin causes a 0.1% frequency error. VSET is approximately 650mV at 25°C, but varies with Similarly, 500M of leakage resistance across RSET temperature. This behavior is shown in the Typical Perfor- (1000 • RSET) causes the same 0.1% error. mance Characteristics. Achieving the highest accuracy requires controlling po- Power can be minimized by maximizing RSET, minimizing tential leakage paths. PC board leakage is aggravated by the load on the OUT pin and operating at lower frequen- both dirt and moisture. Effective cleaning is a good first cies. Figure 9 shows total supply current vs frequency step to minimizing leakage. under typical conditions. Below 100kHz the load current is Another effective method for controlling leakage is to shunt negligible for the 5pF load shown. the leakage current away from the sensitive node through a low impedance path. The LTC6907 provides a signal on the GRD pin for this purpose. Figure 10 shows a PC board 6907fa 8
U U W U APPLICATIO S I FOR ATIO Selecting R
10000
SET and the Divider Ratio
÷1 ÷3 The LTC6907 contains a master oscillator followed by a ÷10 digital divider (see Block Diagram). RSET determines the 1000 master oscillator frequency and the three level DIV pin sets the divider ratio, N. The range of frequencies accessible in each divider ratio overlap, as shown in Figure 7. This figure is derived from the equations in Table 1.
For any
100
given frequency, power can be minimized by minimiz-
OUTPUT FREQUENCY (kHz)
ing the master oscillator frequency. This implies maxi- mizing R
10
SET and using the lowest possible divider ratio,
10 100 1000
N
. The relationship between RSET, N and the unloaded RSET (kΩ) power consumption is shown in Figure 8. The supply 6907 F07 current decreases for large values of R
Figure 7. R
SET. Refer to the
SET vs Desired Output Frequency
section titled “Jitter and Divide Ratio.” 160 CLOAD = 0
Minimizing Power Consumption
140 ISUPPLY V+ = 3V DIV = –:1 120 TA = 25°C The supply current of the LTC6907 has four current µA) 100 components: 80 • Constant (Independent V+, ƒOUT and CLOAD) 60 • Proportional to ISET (which is the current in RSET) SUPPLY CURRENT ( 40 • Proportional to V+, ƒOUT and CLOAD 20 • Proportional to V+ and R 0 LOAD 10 100 1000 RSET (kΩ) An approximate expression for the total supply current is: 6907 F08 V+
Figure 8. Unloaded Supply Current vs RSET
I+ ≅ 7 A µ + 6 •I + V+ • ƒ • (C + p 5 F)+ SET OUT LOAD 2 • RLOAD
Guarding Against PC Board Leakage
o or, in terms of VSET, The LTC6907 uses relatively large resistance values for V V+ I+ 7 A SET 6 • V+ ≅ µ + + • ƒ • (C + p 5 F R )+ SET to minimize power consumption. For RSET = 500k, R OUT LOAD SET 2 • RLOAD the SET pin current is typically only 13µA. Thus, only 13nA leaking into the SET pin causes a 0.1% frequency error. VSET is approximately 650mV at 25°C, but varies with Similarly, 500M of leakage resistance across RSET temperature. This behavior is shown in the Typical Perfor- (1000 • RSET) causes the same 0.1% error. mance Characteristics. Achieving the highest accuracy requires controlling po- Power can be minimized by maximizing RSET, minimizing tential leakage paths. PC board leakage is aggravated by the load on the OUT pin and operating at lower frequen- both dirt and moisture. Effective cleaning is a good first cies. Figure 9 shows total supply current vs frequency step to minimizing leakage. under typical conditions. Below 100kHz the load current is Another effective method for controlling leakage is to shunt negligible for the 5pF load shown. the leakage current away from the sensitive node through a low impedance path. The LTC6907 provides a signal on the GRD pin for this purpose. Figure 10 shows a PC board 6907fa 8