Datasheet LTC6905-XXX (Analog Devices) - 6

LTC6905-XXX Series
U U W U APPLICATIO S I FOR ATIO START-UP TIME
then the oscillator frequency may show an additional error if the switching frequency is 1.4MHz (80MHz/64). The start-up and settling time to within 1% of the final The magnitude of this effect is heavily dependent on frequency is typically 100µs. supply bypass and routing.
MAXIMUM OUTPUT LOAD JITTER AND POWER SUPPLY NOISE
The LTC6905 output (Pin 5) can drive a capacitive load If the LTC6905 is powered by a supply that has frequency (CLOAD) of 5pF or more. Performance driving a CLOAD content equal to the output frequency then the output jitter greater than 5pF depends on the oscillator’s frequency may increase. In addition, power supply ripple in excess of (fOSC) and output resistance (ROUT). The output rise time 20mV at any frequency may increase jitter. or fall time due to ROUT and CLOAD is equal to 2.2 • ROUT • CLOAD (from 10% to 90% of the rise or fall transition). If the Higher divide ratios will result in lower percentage jitter. total output rise time plus fall time is arbitrarily specified For example, jitter percentage of the LTC6905-80 operat- to be equal to or less than 20% of the oscillator’s period (1/ ing at 20MHz is lower than for the same part operating at fOSC), then the maximum output CLOAD in picofarads (pF) 80MHz. Please consult the Jitter vs Frequency graph should be equal to or less than [45454/(ROUT • fOSC)] showing jitter at various divider ratios. (ROUT in ohms and fOSC in MHz). Example: An LTC6905-100 is operating with a 3V power
LTC6905 SUGGESTED CRITICAL COMPONENT
supply and is set for a f
LAYOUT
OSC = 50MHz. R In order to provide the specified performance, it is re- OUT with V+ = 3V is 27Ω (using the ROUT vs V+ graph in the Typical Performance Characteristics). quired that the supply bypass capacitor be placed as close as possible to the LTC6905. The following additional rules The maximum output CLOAD should be equal to or less should be followed for best performance: than [45454/(27 • 50)] = 33.6pF. 1) The bypass capacitor must be placed as close as The lowest resistive load Pin 5 can drive can be calculated possible to the LTC6905, and no vias should be placed using the minimum high level output voltage in the Elec- between the capacitor and the LTC6905. The bypass trical Characteristics. With a V+ equal to 5.5V and 4mA capacitor must be on the same side of the circuit board output current, the minimum high level output voltage is as the LTC6905. 5.2V and the lowest resistive load Pin 5 can drive is 1.30k (5.2V/4mA). With a V+ equal to 2.7V and 4mA output 2) If a ground plane is used, the connection of the LTC6905 current, the minimum high level output voltage is 2.4V and to the ground plane should be as close as possible to the the lowest resistive load Pin 5 can drive is 600Ω (2.4V/4mA). LTC6905 GND pin and should be composed of multiple, high current capacity vias.
FREQUENCY ACCURACY AND POWER SUPPLY NOISE
The frequency accuracy of the LTC6905 may be affected when its power supply generates noise with frequency contents equal to f C MO/64 or its multiples. fMO is the highest frequency for an LTC6905-XXX which is with LTC6905 DIV = V+ (÷1). This is also the frequency indicated in the part number (i.e., LTC6905-100, fMO = 100MHz). fMO/64 6905x F02 is the master oscillator control loop frequency. For ex- ample, if the LTC6905-80 with a master oscillator fre-
Figure 2. LTC6905 Suggested Critical Component Layout
quency of 80MHz is powered by a switching regulator, 6905xfa 6