Datasheet LTC6900 (Analog Devices) - 8
| Hersteller | Analog Devices |
| Beschreibung | Low Power, 1kHz to 20MHz Resistor Set SOT-23 Oscillator |
| Seiten / Seite | 12 / 8 — APPLICATIONS INFORMATION. POWER SUPPLY REJECTION. START-UP TIME. Low … |
| Dateiformat / Größe | PDF / 164 Kb |
| Dokumentensprache | Englisch |
APPLICATIONS INFORMATION. POWER SUPPLY REJECTION. START-UP TIME. Low Frequency Supply Rejection (Voltage Coeffi cient)
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LTC6900
APPLICATIONS INFORMATION POWER SUPPLY REJECTION START-UP TIME
The start-up time and settling time to within 1% of the
Low Frequency Supply Rejection (Voltage Coeffi cient)
fi nal value can be estimated by tSTART ≅ RSET(3.7μs/kΩ) Figure 5 shows the output frequency sensitivity to power + 10μs. Note the start-up time depends on RSET and it is supply voltage at several different temperatures. The independent from the setting of the divider pin. For in- LTC6900 has a guaranteed voltage coeffi cient of 0.1%/V stance with RSET = 100k, the LTC6900 will settle with 1% but, as Figure 5 shows, the typical supply sensitivity is of its 200kHz fi nal value (N = 10) in approximately 380μs. twice as low. Figure 6 shows start-up times for various RSET resistors.
High Frequency Power Supply Rejection
Figure 7 shows an application where a second set resistor RSET2 is connected in parallel with set resistor RSET1 via The accuracy of the LTC6900 may be affected when its switch S1. When switch S1 is open, the output frequency power supply generates signifi cant noise with a frequency of the LTC6900 depends on the value of the resistor RSET1. content in the vicinity of the programmed value of fOSC. If a When switch S1 is closed, the output frequency of the switching power supply is used to power the LTC6900, and LTC6900 depends on the value of the parallel combination if the ripple of the power supply is more than 20mV, make of RSET1 and RSET2. sure the switching frequency and its harmonics are not related to the output frequency of the LTC6900. Otherwise, The start-up time and settling time of the LTC6900 with the oscillator may show additional frequency error. switch S1 open (or closed) is described by tSTART shown above. Once the LTC6900 starts and settles, and switch If the LTC6900 is powered by a switching regulator and S1 closes (or opens), the LTC6900 will settle to its new the switching frequency or its harmonics coincide with output frequency within approximately 70μs. the output frequency of the LTC6900, the jitter of the oscillator output may be affected. This phenomenon will
Jitter
become noticeable if the switching regulator exhibits The Peak-to-Peak Jitter vs Output Frequency graph, in the ripples beyond 30mV. Typical Performance Characteristics section, shows the typical clock jitter as a function of oscillator frequency and power supply voltage. The capacitance from the SET pin, (Pin 3), to ground must be less than 10pF. If this require- ment is not met, the jitter will increase. 0.15 70 RSET = 63.2k TA = 25°C PIN 4 = FLOATING (÷10) 60 V+ = 5V 0.10 50 25°C 40 –40°C 0.05 30 85°C 20 400k 0 FREQUENCY ERROR (%) 10 FREQUENCY DEVIATION (%) 63.2k 0 20k –0.05 –10 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0 200 400 600 800 1000 SUPPLY VOLTAGE (V) TIME AFTER POWER APPLIED (μs) 6900 F05 6900 F06
Figure 5. Supply Sensitivity Figure 6. Start-Up Time
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APPLICATIONS INFORMATION POWER SUPPLY REJECTION START-UP TIME
The start-up time and settling time to within 1% of the
Low Frequency Supply Rejection (Voltage Coeffi cient)
fi nal value can be estimated by tSTART ≅ RSET(3.7μs/kΩ) Figure 5 shows the output frequency sensitivity to power + 10μs. Note the start-up time depends on RSET and it is supply voltage at several different temperatures. The independent from the setting of the divider pin. For in- LTC6900 has a guaranteed voltage coeffi cient of 0.1%/V stance with RSET = 100k, the LTC6900 will settle with 1% but, as Figure 5 shows, the typical supply sensitivity is of its 200kHz fi nal value (N = 10) in approximately 380μs. twice as low. Figure 6 shows start-up times for various RSET resistors.
High Frequency Power Supply Rejection
Figure 7 shows an application where a second set resistor RSET2 is connected in parallel with set resistor RSET1 via The accuracy of the LTC6900 may be affected when its switch S1. When switch S1 is open, the output frequency power supply generates signifi cant noise with a frequency of the LTC6900 depends on the value of the resistor RSET1. content in the vicinity of the programmed value of fOSC. If a When switch S1 is closed, the output frequency of the switching power supply is used to power the LTC6900, and LTC6900 depends on the value of the parallel combination if the ripple of the power supply is more than 20mV, make of RSET1 and RSET2. sure the switching frequency and its harmonics are not related to the output frequency of the LTC6900. Otherwise, The start-up time and settling time of the LTC6900 with the oscillator may show additional frequency error. switch S1 open (or closed) is described by tSTART shown above. Once the LTC6900 starts and settles, and switch If the LTC6900 is powered by a switching regulator and S1 closes (or opens), the LTC6900 will settle to its new the switching frequency or its harmonics coincide with output frequency within approximately 70μs. the output frequency of the LTC6900, the jitter of the oscillator output may be affected. This phenomenon will
Jitter
become noticeable if the switching regulator exhibits The Peak-to-Peak Jitter vs Output Frequency graph, in the ripples beyond 30mV. Typical Performance Characteristics section, shows the typical clock jitter as a function of oscillator frequency and power supply voltage. The capacitance from the SET pin, (Pin 3), to ground must be less than 10pF. If this require- ment is not met, the jitter will increase. 0.15 70 RSET = 63.2k TA = 25°C PIN 4 = FLOATING (÷10) 60 V+ = 5V 0.10 50 25°C 40 –40°C 0.05 30 85°C 20 400k 0 FREQUENCY ERROR (%) 10 FREQUENCY DEVIATION (%) 63.2k 0 20k –0.05 –10 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0 200 400 600 800 1000 SUPPLY VOLTAGE (V) TIME AFTER POWER APPLIED (μs) 6900 F05 6900 F06
Figure 5. Supply Sensitivity Figure 6. Start-Up Time
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