Datasheet AD641 (Analog Devices) - 8

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AD641
Transistors Q3 through Q6 form the full wave detector, whose
2.5
output is buffered by the cascodes Q9 and Q10. For zero input
+25
8
C 1 0
Q3 and Q5 conduct only a small amount (a total of about 32 µA)
–55
8
C 2.0 –1
of the 565 µA tail currents supplied to pairs Q3–Q4 and Q5–Q6.
+85
8
C +125
8
C –2
This “pedestal” current flows in output cascode Q9 to the LOG
1.5
OUT node (Pin 14). When driven to the peak output of the preceding stage, Q3 or Q5 (depending on signal polarity) con-
1.0
ducts most of the tail current, and the output rises to 532 µA. The LOG OUT current has thus changed by 500 µA as the input has changed from zero to its maximum value. Since the
0.5 OUTPUT CURRENT – mA
detectors are spaced at 10 dB intervals, the output increases by
ABSOLUTE ERROR – dB
50 µA/dB, or 1 mA per decade. This scaling parameter is trimmed
0
to absolute accuracy using a 2 kHz square wave. At frequencies near the system bandwidth, the slope is reduced due to the
–0.5 0.1 10 100 1000 10000
reduced output of the limiter stages, but it is still relatively in-
INPUT VOLTAGE – mV
sensitive to temperature variations so that a simple external slope adjustment can restore scaling accuracy. Figure 19. Logarithmic Output and Absolute Error vs. DC or Square Wave Input at TA = –55°C, +25°C, +85°C and The intercept position bias generator (Figure 17) removes the +125°C. Input via On-Chip Attenuator pedestal current from the summed detector outputs. It is ad- justed during manufacture such that the output (flowing into showing the outputs at temperatures of –55°C, +25°C and Pin 14) is 1 mA when a 2 kHz square-wave input of exactly +125°C. While the slope and intercept are seen to be little af- ±10 mV is applied to the AD641. This places the dc intercept at fected by temperature, there is a lateral shift in the end points of precisely 1 mV. The LOG COM output (Pin 13) is the comple- the “linear” region of the transfer function, which reduces the ment of LOG OUT. It also has a 1 mV intercept, but with an effective dynamic range. inverted slope of –1 mA/decade. Because its pedestal is very The on chip attenuator can be used to handle input levels 20 dB large (equivalent to about 100 dB), its intercept voltage is not higher, that is, from ± 7.5 mV to ± 2 V for dc or square wave guaranteed. The intercept positioning currents include a special inputs. It is specially designed to have a positive temperature internal temperature compensation (ITC) term which can be coefficient and is trimmed to position the intercept at 10 mV dc disabled by connecting Pin 8 to ground. (or –24 dBm for a sinusoidal input) over the full temperature The logarithmic function of the AD641 is absolutely calibrated range. When using the attenuator the internal bias compensa- to within ± 0.3 dB (or ± 15 µA) for 2 kHz square-wave inputs of tion should be disabled by grounding Pin 8. Figure 19 shows ±1 mV to ±100 mV, and to within ±1 dB between ±750 µV and the output at –55°C, +25°C, +85°C and +125°C for a single, ±200 mV. Figure 18 is a typical plot of the dc transfer function, AD641 with the attenuator in use; the curves overlap almost perfectly, and the lateral shift in the transfer function does not occur. Therefore, the full dynamic range is available at all temperatures.
2.5 3
The output of the final limiter is available in differential form at
+125
8
C 2
Pins 10 and 11. The output impedance is 75 Ω to ground from
2.0 +25
8
C 1 –55
8
C
either pin. For most input levels, this output will appear to have
0
roughly a square waveform. The signal path may be extended
1.5 –1 –55
8
C
using these outputs (see OPERATION OF CASCADED
+25
8
C –2 +125
8
C
AD641s). The logarithmic outputs from two or more AD641s
1.0 ABSOLUTE ERROR – dB
can be directly summed with full accuracy. A pair of 1 kΩ applications resistors, RG1 and RG2 (Figure 17)
0.5
are accessed via Pins 15, 16 and 17. These can be used to con-
OUTPUT CURRENT – mA
vert an output current to a voltage, with a slope of 1 V/decade
0
(using one resistor), 2 V/decade (both resistors in series) or 0.5 V/decade (both in parallel). Using all the resistors from two
–0.5
AD641s (for example, in a cascaded configuration) ten slope
0.1 1.0 10.0 100.0 1000.0
options from 0.25 V to 4 V/decade are available.
INPUT VOLTAGE – mV
Figure 18. Logarithmic Output and Absolute Error vs. DC or Square Wave Input at TA = –55°C, +25°C, and +125°C, Input Direct to Pins 1 and 20 REV. D –7– Document Outline FEATURES PRODUCT DESCRIPTION PIN CONFIGURATIONS AD641--SPECIFICATIONS ELECTRICAL CHARACTERISTICS THERMAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS ESD CAUTION REVISION HISTORY AD641--TYPICAL DC PERFORMANCE CHARACTERISTICS TYPICAL AC PERFORMANCE CHARACTERISTICS CIRCUIT DESCRIPTION CIRCUIT OPERATION FUNDAMENTALS OF LOGARITHMIC CONVERSION INTERCEPT STABILIZATION CONVERSION RANGE EFFECT OF WAVEFORM ON INTERCEPT LOGARITHMIC CONFORMANCE AND WAVEFORM SIGNAL MAGNITUDE INTERCEPT AND LOGARITHMIC OFFSET OPERATION OF A SINGLE AD641 ACTIVE CURENT-TO-VOLTAGE CONVERSION EFFECT OF FREQUENCY ON CALIBRATION SOURCE RESISTANCE AND INPUT OFFSET USING HIGHER SUPPLY VOLTAGES USING THE ATTENUATOR OPERATION OF CASCADED AD641s ELIMINATING THE EFFECT OF FIRST STAGE OFFSET PRACTICAL APPLICATIONS RSSI APPLICATIONS 250 MHz RSSI CONVERTER WITH 58 dB DYNAMIC RANGE OUTLINE DIMENSIONS ORDERING GUIDE