Datasheet AD8314 (Analog Devices) - 10
| Hersteller | Analog Devices |
| Beschreibung | RF Detector / Controller, 100 MHz TO 2.7 GHz, 45 dB |
| Seiten / Seite | 21 / 10 — AD8314. 2.3. 0mA. 2.2. 2mA. SHADING INDICATES. ±3 SIGMA. 2.1. 4mA. 2.0. … |
| Revision | C |
| Dateiformat / Größe | PDF / 440 Kb |
| Dokumentensprache | Englisch |
AD8314. 2.3. 0mA. 2.2. 2mA. SHADING INDICATES. ±3 SIGMA. 2.1. 4mA. 2.0. 6mA. 1.9. 1.8. 1.7. 2.7. 2.8. 2.9. 3.0. 3.1. 3.2. 3.3. 3.4. 3.5. S (V). AVERAGE: 128 SAMPLES
Modelllinie für dieses Datenblatt
AD8314
Textversion des Dokuments
AD8314 2.3 2.3 0mA 2.2 2mA 2.2 SHADING INDICATES ±3 SIGMA 2.1 4mA 2.1 ) ) (V 2.0 (V 2.0 DN DN V 6mA V 1.9 1.9 1.8 1.8 1.7 1.7 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5
22 25 0
2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5
0 6- 6-
V
08 08
S (V) V
01
S (V)
01 Figure 22. Maximum VDN Voltage vs. VS by Load Current Figure 25. Maximum VDN Voltage vs. VS with 3 mA Load
AVERAGE: 128 SAMPLES V AVERAGE: 128 SAMPLES UP VUP 500mV/VERTICAL 200mV PER DIVISION VERTICAL DIVISION VDN VDN GND VDN GND VUP 500mV/VERTICAL V DIVISION UP GND VPOS AND ENABLE 2V PER VERTICAL 2V PER 100ns PER VPOS AND ENABLE DIVISION VERTICAL HORIZONTAL 1µs PER DIVISION DIVISION GND HORIZONTAL
23
GND
26
DIVISION
0 0 6- 6- 08 08 01 01 Figure 23. Power-On and Power-Off Response, Measurement Mode Figure 26. Power-On Response, VDN, Controller Mode with VSET Held Low
TRIG TRIG HP8648B 10MHz REF OUTPUT EXT TRIG HP8116A OUT HP8648B 10MHz REF OUTPUT EXT TRIG HP8112A OUT SIGNAL PULSE SIGNAL PULSE GENERATOR GENERATOR GENERATOR GENERATOR –33dBV RF OUT PULSE RF OUT PULSE OUT OUT AD811 AD811 49.9Ω 49.9Ω 1 RFIN VPOS 8 732Ω 1 RFIN VPOS 8 732Ω TRIG TRIG 52.3Ω TEK P6204 52.3Ω TEK P6204 2 ENBL V_DN 7 FET PROBE TEK 2 ENBL V_DN 7 FET PROBE TEK AD8314 TDS784C AD8314 TDS784C TEK P6204 SCOPE SCOPE 3 VSET V_UP 6 FET PROBE 0.2 3 VSET V_UP 6 NC NC 4 FLTR COMM 5 NC 4 FLTR COMM 5
24 27 0 0 6- 6-
NC = NO CONNECT
08
NC = NO CONNECT
08 01 01 Figure 24. Test Setup for Power-On and Power-Off Response Figure 27. Test Setup for Power-On Response at V_DN Output, Controller Mode with VSET Pin Held Low Rev. B | Page 9 of 20 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION INVERTED OUTPUT APPLICATIONS BASIC CONNECTIONS TRANSFER FUNCTION IN TERMS OF SLOPE AND INTERCEPT dBV VS. dBm FILTER CAPACITOR OPERATING IN CONTROLLER MODE POWER-ON AND ENABLE GLITCH INPUT COUPLING OPTIONS INCREASING THE LOGARITHMIC SLOPE IN MEASUREMENT MODE EFFECT OF WAVEFORM TYPE ON INTERCEPT MOBILE HANDSET POWER CONTROL EXAMPLES OPERATION AT 2.7 GHz USING THE LFCSP PACKAGE EVALUATION BOARD OUTLINE DIMENSIONS ORDERING GUIDE
22 25 0
2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5
0 6- 6-
V
08 08
S (V) V
01
S (V)
01 Figure 22. Maximum VDN Voltage vs. VS by Load Current Figure 25. Maximum VDN Voltage vs. VS with 3 mA Load
AVERAGE: 128 SAMPLES V AVERAGE: 128 SAMPLES UP VUP 500mV/VERTICAL 200mV PER DIVISION VERTICAL DIVISION VDN VDN GND VDN GND VUP 500mV/VERTICAL V DIVISION UP GND VPOS AND ENABLE 2V PER VERTICAL 2V PER 100ns PER VPOS AND ENABLE DIVISION VERTICAL HORIZONTAL 1µs PER DIVISION DIVISION GND HORIZONTAL
23
GND
26
DIVISION
0 0 6- 6- 08 08 01 01 Figure 23. Power-On and Power-Off Response, Measurement Mode Figure 26. Power-On Response, VDN, Controller Mode with VSET Held Low
TRIG TRIG HP8648B 10MHz REF OUTPUT EXT TRIG HP8116A OUT HP8648B 10MHz REF OUTPUT EXT TRIG HP8112A OUT SIGNAL PULSE SIGNAL PULSE GENERATOR GENERATOR GENERATOR GENERATOR –33dBV RF OUT PULSE RF OUT PULSE OUT OUT AD811 AD811 49.9Ω 49.9Ω 1 RFIN VPOS 8 732Ω 1 RFIN VPOS 8 732Ω TRIG TRIG 52.3Ω TEK P6204 52.3Ω TEK P6204 2 ENBL V_DN 7 FET PROBE TEK 2 ENBL V_DN 7 FET PROBE TEK AD8314 TDS784C AD8314 TDS784C TEK P6204 SCOPE SCOPE 3 VSET V_UP 6 FET PROBE 0.2 3 VSET V_UP 6 NC NC 4 FLTR COMM 5 NC 4 FLTR COMM 5
24 27 0 0 6- 6-
NC = NO CONNECT
08
NC = NO CONNECT
08 01 01 Figure 24. Test Setup for Power-On and Power-Off Response Figure 27. Test Setup for Power-On Response at V_DN Output, Controller Mode with VSET Pin Held Low Rev. B | Page 9 of 20 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION INVERTED OUTPUT APPLICATIONS BASIC CONNECTIONS TRANSFER FUNCTION IN TERMS OF SLOPE AND INTERCEPT dBV VS. dBm FILTER CAPACITOR OPERATING IN CONTROLLER MODE POWER-ON AND ENABLE GLITCH INPUT COUPLING OPTIONS INCREASING THE LOGARITHMIC SLOPE IN MEASUREMENT MODE EFFECT OF WAVEFORM TYPE ON INTERCEPT MOBILE HANDSET POWER CONTROL EXAMPLES OPERATION AT 2.7 GHz USING THE LFCSP PACKAGE EVALUATION BOARD OUTLINE DIMENSIONS ORDERING GUIDE