Datasheet AD8364 (Analog Devices) - 3
| Hersteller | Analog Devices |
| Beschreibung | LF to 2.7 GHz, DUAL 60 dB TruPwr™ Detector |
| Seiten / Seite | 45 / 3 — AD8364. Data Sheet. TABLE OF CONTENTS. REVISION HISTORY 8/2016—Rev. B to … |
| Revision | C |
| Dateiformat / Größe | PDF / 1.6 Mb |
| Dokumentensprache | Englisch |
AD8364. Data Sheet. TABLE OF CONTENTS. REVISION HISTORY 8/2016—Rev. B to Rev. C. 1/2012—Rev. A to Rev. B
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AD8364 Data Sheet TABLE OF CONTENTS
Features .. 1 Controller Mode ... 22 Applications ... 1 RF Measurement Mode Basic Connections ... 23 Functional Block Diagram .. 1 Controller Mode Basic Connections ... 24 General Description ... 1 Constant Output Power Operation .. 27 Revision History ... 2 Gain-Stable Transmitter/Receiver .. 29 Specifications ... 3 Temperature Compensation Adjustment.. 31 Absolute Maximum Ratings .. 7 Device Calibration and Error Calculation .. 31 ESD Caution .. 7 Selecting Calibration Points to Improve Accuracy over a Pin Configuration and Function Descriptions ... 8 Reduced Range ... 32 Typical Performance Characteristics ... 9 Channel Isolation ... 34 Theory of Operation .. 18 Altering the Slope ... 35 Square Law Detector and Amplitude Target... 19 Choosing the Right Value for CHP[A, B] and CLP[A, B] .. 36 RF Input Interface .. 19 RF Burst Response Time ... 36 Offset Compensation ... 19 Single-Ended Input Operation ... 36 Temperature Sensor Interface ... 20 Printed Circuit Board Considerations ... 37 VREF Interface ... 20 Package Considerations ... 37 Power-Down Interface ... 20 Description of Characterization ... 38 VST[A, B] Interface .. 20 Basis for Error Calculations .. 38 OUT[A, B, P, N] Outputs .. 21 Evaluation Board .. 40 Measurement Channel Difference Output Using OUT[P, N] Outline Dimensions ... 41 ... 22 Ordering Guide .. 41
REVISION HISTORY 8/2016—Rev. B to Rev. C
Deleted Figure 85 and Figure 86; Renumbered Sequential y ... 41 Updated Outline Dimensions ... 41 Updated Outline Dimensions ... 41 Changes to Ordering Guide .. 41 Changes to Ordering Guide .. 41 Deleted Table 7, AD8364-EVAL-500 Evaluation Board
1/2012—Rev. A to Rev. B
Configuration Options and AD8364-EVAL-2140 Evaluation Change to Figure 84 ... 40 Board Configuration Options; Renumbered Sequentially ... 42 Deleted Evaluation Boards Section and Figure 87 ... 44
11/2011—Rev. 0 to Rev. A
Deleted Figure 88 .. 45 Changes to Figure 2 .. 8 Deleted Assembly Drawings Section, Figure 89, and Changes to Automatic Power Control Section ... 24 Figure 90 .. 46 Replaced Evaluation and Characterization Circuit Board Layouts Section with Evaluation Board Section ... 40
4/2005—Revision 0: Initial Version
Changes to Figure 84 .. 40 Rev. C | Page 2 of 44 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION SQUARE LAW DETECTOR AND AMPLITUDE TARGET RF INPUT INTERFACE OFFSET COMPENSATION TEMPERATURE SENSOR INTERFACE VREF INTERFACE POWER-DOWN INTERFACE VST[A, B] INTERFACE OUT[A, B, P, N] OUTPUTS MEASUREMENT CHANNEL DIFFERENCE OUTPUT USING OUT[P, N] CONTROLLER MODE RF MEASUREMENT MODE BASIC CONNECTIONS CONTROLLER MODE BASIC CONNECTIONS Automatic Power Control Automatic Gain Control CONSTANT OUTPUT POWER OPERATION GAIN-STABLE TRANSMITTER/RECEIVER TEMPERATURE COMPENSATION ADJUSTMENT DEVICE CALIBRATION AND ERROR CALCULATION SELECTING CALIBRATION POINTS TO IMPROVE ACCURACY OVER A REDUCED RANGE CHANNEL ISOLATION ALTERING THE SLOPE CHOOSING THE RIGHT VALUE FOR CHP[A, B] AND CLP[A, B] RF BURST RESPONSE TIME SINGLE-ENDED INPUT OPERATION PRINTED CIRCUIT BOARD CONSIDERATIONS PACKAGE CONSIDERATIONS DESCRIPTION OF CHARACTERIZATION BASIS FOR ERROR CALCULATIONS EVALUATION BOARD OUTLINE DIMENSIONS ORDERING GUIDE
AD8364 Data Sheet TABLE OF CONTENTS
Features .. 1 Controller Mode ... 22 Applications ... 1 RF Measurement Mode Basic Connections ... 23 Functional Block Diagram .. 1 Controller Mode Basic Connections ... 24 General Description ... 1 Constant Output Power Operation .. 27 Revision History ... 2 Gain-Stable Transmitter/Receiver .. 29 Specifications ... 3 Temperature Compensation Adjustment.. 31 Absolute Maximum Ratings .. 7 Device Calibration and Error Calculation .. 31 ESD Caution .. 7 Selecting Calibration Points to Improve Accuracy over a Pin Configuration and Function Descriptions ... 8 Reduced Range ... 32 Typical Performance Characteristics ... 9 Channel Isolation ... 34 Theory of Operation .. 18 Altering the Slope ... 35 Square Law Detector and Amplitude Target... 19 Choosing the Right Value for CHP[A, B] and CLP[A, B] .. 36 RF Input Interface .. 19 RF Burst Response Time ... 36 Offset Compensation ... 19 Single-Ended Input Operation ... 36 Temperature Sensor Interface ... 20 Printed Circuit Board Considerations ... 37 VREF Interface ... 20 Package Considerations ... 37 Power-Down Interface ... 20 Description of Characterization ... 38 VST[A, B] Interface .. 20 Basis for Error Calculations .. 38 OUT[A, B, P, N] Outputs .. 21 Evaluation Board .. 40 Measurement Channel Difference Output Using OUT[P, N] Outline Dimensions ... 41 ... 22 Ordering Guide .. 41
REVISION HISTORY 8/2016—Rev. B to Rev. C
Deleted Figure 85 and Figure 86; Renumbered Sequential y ... 41 Updated Outline Dimensions ... 41 Updated Outline Dimensions ... 41 Changes to Ordering Guide .. 41 Changes to Ordering Guide .. 41 Deleted Table 7, AD8364-EVAL-500 Evaluation Board
1/2012—Rev. A to Rev. B
Configuration Options and AD8364-EVAL-2140 Evaluation Change to Figure 84 ... 40 Board Configuration Options; Renumbered Sequentially ... 42 Deleted Evaluation Boards Section and Figure 87 ... 44
11/2011—Rev. 0 to Rev. A
Deleted Figure 88 .. 45 Changes to Figure 2 .. 8 Deleted Assembly Drawings Section, Figure 89, and Changes to Automatic Power Control Section ... 24 Figure 90 .. 46 Replaced Evaluation and Characterization Circuit Board Layouts Section with Evaluation Board Section ... 40
4/2005—Revision 0: Initial Version
Changes to Figure 84 .. 40 Rev. C | Page 2 of 44 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION SQUARE LAW DETECTOR AND AMPLITUDE TARGET RF INPUT INTERFACE OFFSET COMPENSATION TEMPERATURE SENSOR INTERFACE VREF INTERFACE POWER-DOWN INTERFACE VST[A, B] INTERFACE OUT[A, B, P, N] OUTPUTS MEASUREMENT CHANNEL DIFFERENCE OUTPUT USING OUT[P, N] CONTROLLER MODE RF MEASUREMENT MODE BASIC CONNECTIONS CONTROLLER MODE BASIC CONNECTIONS Automatic Power Control Automatic Gain Control CONSTANT OUTPUT POWER OPERATION GAIN-STABLE TRANSMITTER/RECEIVER TEMPERATURE COMPENSATION ADJUSTMENT DEVICE CALIBRATION AND ERROR CALCULATION SELECTING CALIBRATION POINTS TO IMPROVE ACCURACY OVER A REDUCED RANGE CHANNEL ISOLATION ALTERING THE SLOPE CHOOSING THE RIGHT VALUE FOR CHP[A, B] AND CLP[A, B] RF BURST RESPONSE TIME SINGLE-ENDED INPUT OPERATION PRINTED CIRCUIT BOARD CONSIDERATIONS PACKAGE CONSIDERATIONS DESCRIPTION OF CHARACTERIZATION BASIS FOR ERROR CALCULATIONS EVALUATION BOARD OUTLINE DIMENSIONS ORDERING GUIDE