Datasheet AD8557 (Analog Devices) - 4

Data Sheet AD8557 SPECIFICATIONS
VDD = 5.0 V, VSS = 0.0 V, VCM = 2.5 V, VOUT = 2.5 V, gain = 28, TA = −40°C to +125°C, unless otherwise specified.
Table 1. Parameter Symbol Test Conditions/Comments Min Typ Max Unit
INPUT STAGE Input Offset Voltage VOS 2 12 μV Input Offset Voltage Drift TCVOS 27 65 nV/°C Input Bias Current IB 10 18 25 nA Input Offset Current IOS 1 4 nA Input Voltage Range 0.6 3.8 V Common-Mode Rejection Ratio CMRR VCM = 0.9 V to 3.6 V, AV = 28 75 85 dB VCM = 0.9 V to 3.6 V, AV = 1300 96 112 dB Linearity VOUT = 0.2 V to 3.4 V 20 ppm VOUT = 0.2 V to 4.8 V 1000 ppm Differential Gain Accuracy Second stage gain = 10 to 70 1.6 % Differential Gain Accuracy Second stage gain = 100 to 250 2.5 % Differential Gain Temperature Coefficient Second stage gain = 10 to 250 15 40 ppm/°C DAC Accuracy Offset codes = 8 to 248 0.7 0.8 % Ratiometricity Offset codes = 8 to 248 50 ppm Output Offset Offset codes = 8 to 248 5 35 mV Temperature Coefficient 20 80 ppm FS/°C VCLAMP Clamp Input Bias Current ICLAMP 1.25 V to 5.0 V 200 nA Clamp Input Voltage Range 1.25 5.0 V OUTPUT STAGE Short-Circuit Current ISC Source −45 −25 mA ISC Sink 40 55 mA Output Voltage, Low VOL RL = 10 kΩ to 5 V 30 mV Output Voltage, High VOH RL = 10 kΩ to 0 V 4.94 V POWER SUPPLY Supply Current ISY VPOS = VNEG = 2.5 V, 1.8 mA VDAC code = 128, VOUT = 2.5 V Power Supply Rejection Ratio PSRR VDD = 2.7 V to 5.5 V 105 125 dB DYNAMIC PERFORMANCE Gain Bandwidth Product GBP First gain stage, TA = 25°C 2 MHz Second gain stage, TA = 25°C 8 MHz Settling Time ts To 0.1%, 4 V output step 8 μs NOISE PERFORMANCE Input Referred Noise f = 1 kHz, TA = 25°C 32 nV/√Hz Low Frequency Noise en p-p f = 0.1 Hz to 10 Hz, TA = 25°C 0.5 μV p-p Total Harmonic Distortion THD VIN = 16.75 mV rms, f = 1 kHz, −100 dB TA = 25°C DIGITAL INTERFACE Input Current 2 μA DIGIN Pulse Width to Load 0 tw0 TA = 25°C 0.05 10 μs DIGIN Pulse Width to Load 1 tw1 TA = 25°C 50 μs Time Between Pulses at DIGIN tws TA = 25°C 10 μs DIGIN Low TA = 25°C 0.2 × VDD V DIGIN High TA = 25°C 0.8 × VDD V DIGOUT Logic 0 TA = 25°C 0.2 × VDD V DIGOUT Logic 1 TA = 25°C 0.8 × VDD V Rev. D | Page 3 of 24 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION GAIN VALUES OPEN WIRE FAULT DETECTION SHORTED WIRE FAULT DETECTION FLOATING VPOS, VNEG, OR VCLAMP FAULT DETECTION DEVICE PROGRAMMING Digital Interface Initial State Simulation Mode Programming Mode Read Mode Sense Current Programming Procedure Determining Optimal Gain and Offset Codes OUTLINE DIMENSIONS ORDERING GUIDE AUTOMOTIVE PRODUCTS