Datasheet ADA4922-1 (Analog Devices) - 6

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Data Sheet ADA4922-1 ABSOLUTE MAXIMUM RATINGS Table 3.
The power dissipated in the package (PD) is the sum of the quiescent power dissipation and the power dissipated in the
Parameter Rating
package due to the load drive for all outputs. The quiescent Supply Voltage 26 V power is the voltage between the supply pins (V Power Dissipation See Figure 3 S) times the quiescent current (I Storage Temperature Range –65°C to +125°C S). The power dissipated due to the load drive depends upon the particular application. For each output, Operating Temperature Range –40°C to +85°C the power due to load drive is calculated by multiplying the load Lead Temperature (Soldering 10 sec) 300°C current by the associated voltage drop across the device. The Junction Temperature 150°C power dissipated due to all of the loads is equal to the sum of Stresses at or above those listed under Absolute Maximum the power dissipation due to each individual load. RMS voltages Ratings may cause permanent damage to the product. This is a and currents must be used in these calculations. stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational Airflow increases heat dissipation, effectively reducing θJA. In section of this specification is not implied. Operation beyond addition, more metal directly in contact with the package leads the maximum operating conditions for extended periods may from metal traces, through holes, ground, and power planes affect product reliability. reduces the θJA. The exposed paddle on the underside of the package must be soldered to a pad on the PCB surface that is
THERMAL RESISTANCE
thermally connected to a copper plane to achieve the specified θJA. θJA is specified for the worst-case conditions, that is, θJA is Figure 3 shows the maximum safe power dissipation in the specified for a device soldered in the circuit board with its packages vs. the ambient temperature for the 8-lead SOIC exposed paddle soldered to a pad on the PCB surface that is (79°C/W) and for the 8-lead LFCSP (81°C/W) on a JEDEC thermally connected to a copper plane, with zero airflow. standard 4-layer board, each with its underside paddle soldered to a pad that is thermally connected to a PCB plane. θ
Table 4. Thermal Resistance
JA values are approximations.
Package Type θJA θJC Unit
8-Lead SOIC with EP on 4-Layer Board 79 25 C/W
3.0
8-Lead LFCSP with EP on 4-Layer Board 81 17 C/W
) W 2.5 ( MAXIMUM POWER DISSIPATION SOIC TION 2.0
The maximum safe power dissipation in the ADA4922-1
LFCSP
package is limited by the associated rise in junction temperature
ISSIPA D R 1.5
(TJ) on the die. At approximately 150°C, which is the glass
E
transition temperature, the plastic changes its properties. Even
POW 1.0
temporarily exceeding this temperature limit can change the
M U
stresses that the package exerts on the die, permanently shifting
XIM A 0.5
the parametric performance of the ADA4922-1. Exceeding a
M
junction temperature of 150°C for an extended period can
0
05681-041 result in changes in the silicon devices potentially causing
–40 –20 0 20 40 60 80
failure.
AMBIENT TEMPERATURE ( C)
Figure 3. Maximum Power Dissipation vs. Temperature for a 4-Layer Board
ESD CAUTION
Rev. A | Page 5 of 19 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE MAXIMUM POWER DISSIPATION ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION APPLICATIONS INFORMATION ADA4922-1 DIFFERENTIAL OUTPUT NOISE MODEL USING THE REF PIN INTERNAL FEEDBACK NETWORK POWER DISSIPATION DISABLE FEATURE DRIVING A DIFFERENTIAL INPUT ADC PRINTED CIRCUIT BOARD LAYOUT CONSIDERATIONS OUTLINE DIMENSIONS ORDERING GUIDE