Datasheet AD8139 (Analog Devices) - 8

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Data Sheet AD8139 ABSOLUTE MAXIMUM RATINGS
The power dissipated in the package (PD) is the sum of the
Table 3.
quiescent power dissipation and the power dissipated in the
Parameter Rating
package due to the load drive for all outputs. The quiescent Supply Voltage 12 V power is the voltage between the supply pins (VS) times the VOCM ±VS quiescent current (IS). The load current consists of differential Power Dissipation See Figure 4 and common-mode currents flowing to the load, as well as Input Common-Mode Voltage ±VS currents flowing through the external feedback networks and Storage Temperature Range −65°C to +125°C the internal common-mode feedback loop. The internal resistor Operating Temperature Range −40°C to +125°C tap used in the common-mode feedback loop places a 1 kΩ Lead Temperature (Soldering 10 sec) 300°C differential load on the output. RMS output voltages should be Junction Temperature 150°C considered when dealing with ac signals. Stresses at or above those listed under Absolute Maximum Airflow reduces θJA. In addition, more metal directly in contact Ratings may cause permanent damage to the product. This is a with the package leads from metal traces, through holes, ground, stress rating only; functional operation of the product at these and power planes reduce the θJA. or any other conditions above those indicated in the operational Figure 4 shows the maximum safe power dissipation in the section of this specification is not implied. Operation beyond package vs. the ambient temperature for the exposed paddle the maximum operating conditions for extended periods may (EP) 8-lead SOIC (θ affect product reliability. JA = 70°C/W) and the 8-lead LFCSP (θJA = 70°C/W) on a JEDEC standard 4-layer board. θJA
THERMAL RESISTANCE
values are approximations. θ
4.0
JA is specified for the worst-case conditions, that is, θJA is specified for device soldered in circuit board for surface-mount packages.
3.5 ) Table 4. (W N 3.0 IO Package Type θ T JA Unit PA 2.5
8-Lead SOIC with EP/4-Layer 70 °C/W
ISSI
8-Lead LFCSP/4-Layer 70 °C/W
D 2.0 ER Maximum Power Dissipation W 1.5 SOIC
The maximum safe power dissipation in the AD8139 package
M PO AND LFCSP MU 1.0
is limited by the associated rise in junction temperature (T
XI
J) on the die. At approximately 150°C, which is the glass transition
MA 0.5
temperature, the plastic changes its properties. Even temporarily
0
exceeding this temperature limit can change the stresses that the
–40 –20 0 20 40 60 80 100 120
055
AMBIENT TEMPERATURE (°C)
package exerts on the die, permanently shifting the parametric 04679- Figure 4. Maximum Power Dissipation vs. Temperature for a 4-Layer Board performance of the AD8139. Exceeding a junction temperature of 175°C for an extended period can result in changes in the silicon devices potential y causing failure.
ESD CAUTION
Rev. C | Page 7 of 26 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAMS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS VS = ±5 V, VOCM = 0 V VS = 5 V, VOCM = 2.5 V ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Maximum Power Dissipation ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TEST CIRCUITS THEORY OF OPERATION TYPICAL CONNECTION AND DEFINITION OF TERMS Output Balance APPLICATIONS INFORMATION ESTIMATING NOISE, GAIN, AND BANDWIDTH WITH MATCHED FEEDBACK NETWORKS Estimating Output Noise Voltage Voltage Gain Feedback Factor Notation Input Common-Mode Voltage Calculating Input Impedance Input Common-Mode Swing Considerations Bandwidth vs. Closed-Loop Gain Estimating DC Errors Other Impact of Mismatches in the Feedback Networks Driving a Capacitive Load Layout Considerations Terminating a Single-Ended Input Exposed Paddle (EP) OUTLINE DIMENSIONS ORDERING GUIDE