Datasheet AD557 (Analog Devices) - 3

AD557–SPECIFICATIONS (@ TA = 25
ⴗ
C, VCC = 5 V unless otherwise noted) Model Min Typ Max Unit ABSOLUTE MAXIMUM RATINGS*
RESOLUTION 8 Bits V RELATIVE ACCURACY CC to Ground . 0 V to 18 V 0°C to 70°C ± 1/2 1 LSB Digital Inputs (Pins 1–10) . 0 V to 7.0 V V OUTPUT OUT . Indefinite Short to Ground Ranges 0 to 2.56 V Momentary Short to VCC Current Source 5 mA Power Dissipation . 450 mW Sink Internal Passive Storage Temperature Range Pull-Down to Ground2 N/P (Plastic) Packages . –25°C to +100°C OUTPUT SETTLING TIME3 0.8 1.5 µs Lead Temperature (Soldering, 10 sec) . 300°C FULL-SCALE ACCURACY4 Thermal Resistance @ 25°C ± 1.5 ± 2.5 LSB Junction to Ambient/Junction to Case T ± MIN to TMAX 2.5 ± 4.0 LSB N/P (Plastic) Packages . 140/55°C/W ZERO ERROR @ 25°C ± 1 LSB *Stresses above those listed under Absolute Maximum Ratings may cause perma- T ± nent damage to the device. This is a stress rating only; functional operation of the MIN to TMAX 3 LSB device at these or any other conditions above those indicated in the operational MONOTONICITY5 section of this specification is not implied. Exposure to absolute maximum rating TMIN to TMAX Guaranteed But Not Tested conditions for extended periods may affect device reliability. DIGITAL INPUTS TMIN to TMAX Input Current ⴞ
100
µA
PIN CONFIGURATIONS
Data Inputs, Voltage Bit On—Logic “1” 2.0 V
DIP
Bit On—Logic “0” 0 0.8 V Control Inputs, Voltage On—Logic “1” 2.0 V
(LSB) BIT 8 1 16 VOUT
On—Logic “0” 0 0.8 V
BIT 7 2 15 VOUT SENSE A
Input Capacitance 4 pF
BIT 6 3 14 VOUT SENSE B AD557
TIMING6
BIT 5 4 13 TOP VIEW GND
tW Strobe Pulsewidth 225 ns
(Not to Scale)
T
BIT 4 5 12 GND
MIN to TMAX
300
ns tDH Data Hold Time 10 ns
BIT 3 6 11 +VCC
TMIN to TMAX
10
ns t
BIT 2 7 10 CS
DS Data Setup Time 225 ns TMIN to TMAX
300
ns
(MSB) BIT 1 8 9 CE
POWER SUPPLY Operating Voltage Range (VCC) 2.56 Volt Range
4.5 5.5
V
PLCC
Current (ICC) 15 25 mA Rejection Ratio
0.03
%/% POWER DISSIPATION, VCC = 5 V 75 125 mW
SENSE A
OPERATING TEMPERATURE RANGE 0 70 °C
OUT OUT BIT 8 (LSB) NC
NOTES
BIT 7 V V
1 Relative Accuracy is defined as the deviation of the code transition points from the
3 2 1 20 19
ideal transfer point on a straight line from the offset to the full scale of the device. See “Measuring Offset Error” on the AD558 data sheet.
BIT 6 4 PIN 1 18 VOUT SENSE B IDENTIFIER
2Passive pull-down resistance is 2 kΩ.
BIT 5 5 17 GND
3Settling time is specified for a positive-going full-scale step to ± 1/2 LSB. Negative-
AD557
going steps to zero are slower, but can be improved with an external pull-down.
NC 6 16 TOP VIEW NC
4The full-scale output voltage is 2.55 V and is guaranteed with a 5 V supply.
BIT 4 7 (Not to Scale) 15 GND
5A monotonic converter has a maximum differential linearity error of ±1 LSB. 6
BIT 3 8 14 +V
See Figure 7.
CC
Specifications shown in
boldface
are tested on all production units at electrical test.
9 10 11 12 13
Specifications subject to change without notice.
NC CE CS BIT 2 NC = NO CONNECT (MSB) BIT 1 ORDERING GUIDE Temperature Package Package Model Range Description Option
AD557JN 0°C to 70°C Plastic DIP N-16 AD557JP 0°C to 70°C Plastic Leaded Chip Carrier P-20A –2– REV. B