Datasheet AD5379 (Analog Devices) - 7

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AD5379 TIMING CHARACTERISTICS SERIAL INTERFACE
VCC = 2.7 V to 5.5 V; VDD = 11.4 V to 16.5 V; VSS = −11.4 V to −16.5 V; VREF(+) = 5 V; VREF(−) = −3.5 V; AGND = DGND = REFGND = 0 V; VBIAS = 5 V, FIFOEN = 0 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 4. Parameter 1 , 2 , 3 Limit at TMIN, TMAX Unit Description
t1 20 ns min SCLK cycle time. t2 8 ns min SCLK high time. t3 8 ns min SCLK low time. t4 10 ns min SYNC falling edge to SCLK falling edge setup time. t 4 5 15 ns min 24th SCLK falling edge to SYNC falling edge. t 4 6 25 ns min Minimum SYNC low time. t7 10 ns min Minimum SYNC high time. t8 5 ns min Data setup time. t9 4.5 ns min Data hold time. t 4, 5 10 30 ns max 24th SCLK falling edge to BUSY falling edge. t11 330 ns max BUSY pulse width low (single-channel update). See Table 10. t 4 12 20 ns min 24th SCLK falling edge to LDAC falling edge. t13 20 ns min LDAC pulse width low. t14 150 ns typ BUSY rising edge to DAC output response time. t15 0 ns min BUSY rising edge to LDAC falling edge. t16 100 ns min LDAC falling edge to DAC output response time. t17 20/30 μs typ/max DAC output settling time. t18 10 ns min CLR pulse width low. t19 350 ns max CLR/RESET pulse activation time. t 6, 7 20 25 ns max SCLK rising edge to sdo valid. t 7 21 5 ns min SCLK falling edge to SYNC rising edge. t 7 22 5 ns min SYNC rising edge to SCLK rising edge. t 7 23 20 ns min SYNC rising edge to LDAC falling edge. t 5 24 30 ns min SYNC rising edge to BUSY falling edge. t25 10 ns min RESET pulse width low. t26 120 μs max RESET time indicated by BUSY low. 1 Guaranteed by design and characterization, not production tested. 2 All input signals are specified with tr = tf = 2 ns (10% to 90% of VCC), and timed from a voltage level of 1.2 V. 3 See Figure 4 and Figure 5. 4 Standalone mode only. 5 This is measured with the load circuit shown in Figure 2. 6 This is measured with the load circuit shown in Figure 3. 7 Daisy-chain mode only.
VCC 200
μ
A IOL R TO L 2.2k
Ω
VOH(min) + VOL(max) OUTPUT 2 PIN CL 50pF TO OUTPUT VOL PIN 200
μ
A IOH CL 50pF
03165-003 03165-002 Figure 3. Load Circuit for SDO Timing Diagram Figure 2. Load Circuit for BUSY Timing Diagram (Serial Interface, Daisy-Chain Mode) Rev. B | Page 6 of 28 Document Outline FEATURES APPLICATIONS TABLE OF CONTENTS GENERAL DESCRIPTION SPECIFICATIONS AC CHARACTERISTICS TIMING CHARACTERISTICS SERIAL INTERFACE PARALLEL INTERFACE ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TERMINOLOGY TYPICAL PERFORMANCE CHARACTERISTICS FUNCTIONAL DESCRIPTION DAC ARCHITECTURE—GENERAL CHANNEL GROUPS TRANSFER FUNCTION VBIAS FUNCTION REFERENCE SELECTION Reference Selection Example CALIBRATION Calibration Example CLEAR FUNCTION Hardware Clear Software Clear /BUSY AND /LDAC FUNCTIONS FIFO VS. NON-FIFO OPERATION /BUSY INPUT FUNCTION POWER-ON RESET FUNCTION /RESET INPUT FUNCTION INCREMENT/DECREMENT FUNCTION INTERFACES PARALLEL INTERFACE / CS Pin /WR Pin REG1, REG0 Pins DB13 to DB0 Pins A7 to A0 Pins SERIAL INTERFACE /SYNC , DIN, SCLK DCEN SDO Standalone Mode Daisy-Chain Mode DATA DECODING ADDRESS DECODING POWER SUPPLY DECOUPLING POWER-ON TYPICAL APPLICATION CIRCUIT OUTLINE DIMENSIONS ORDERING GUIDE