Datasheet AD5380 (Analog Devices) - 7

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AD5380 Data Sheet Parameter AD5380-51 Unit Test Conditions/Comments
LOGIC INPUTS (SDA, SCL ONLY)3 VIH, Input High Voltage 0.7 × DVDD V min SMBus compatible at DVDD < 3.6 V VIL, Input Low Voltage 0.3 × DVDD V max SMBus compatible at DVDD < 3.6 V IIN, Input Leakage Current ±1 µA max VHYST, Input Hysteresis 0.05 × DVDD V min CIN, Input Capacitance 8 pF typ Glitch Rejection 50 ns max Input filtering suppresses noise spikes of less than 50 ns LOGIC OUTPUTS (BUSY, SDO)3 VOL, Output Low Voltage 0.4 V max DVDD = 5 V ± 10%, sinking 200 µA VOH, Output High Voltage DVDD – 1 V min DVDD = 5 V ± 10%, sourcing 200 µA VOL, Output Low Voltage 0.4 V max DVDD = 2.7 V to 3.6 V, sinking 200 µA VOH, Output High Voltage DVDD – 0.5 V min DVDD = 2.7 V to 3.6 V, sourcing 200 µA High Impedance Leakage Current ±1 µA max SDO only High Impedance Output Capacitance 5 pF typ SDO only LOGIC OUTPUT (SDA)3 VOL, Output Low Voltage 0.4 V max ISINK = 3 mA 0.6 V max ISINK = 6 mA Three-State Leakage Current ±1 µA max Three-State Output Capacitance 8 pF typ POWER REQUIREMENTS AVDD 4.5/5.5 V min/max DVDD 2.7/5.5 V min/max Power Supply Sensitivity3 ∆Midscale/∆ΑVDD –85 dB typ AIDD 0.375 mA/channel max Outputs unloaded; boost off; 0.25 mA/channel typ 0.475 mA/channel max Outputs unloaded; boost on; 0.325 mA/channel typ DIDD 1 mA max VIH = DVDD, VIL = DGND AIDD (Power-Down) 20 µA max Typically 100 nA DIDD (Power-Down) 20 µA max Typically 1 µA Power Dissipation 80 mW max Outputs unloaded, boost off, AVDD = DVDD = 5 V 1 AD5380-5 is calibrated using an external 2.5 V reference. Temperature range for all versions: –40°C to +85°C. 2 Accuracy guaranteed from VOUT= 10 mV to AVDD – 50 mV. 3 Guaranteed by characterization, not production tested. 4 Default on the AD5380-5 is 2.5 V. Programmable to 1.25 V via CR12 in the AD5380 control register; operating the AD5380-5 with a 1.25 V reference wil lead to degraded accuracy specifications. Rev. D | Page 6 of 40 Document Outline Features Integrated Functions Applications Functional Block Diagram Table Of Contents Revision History General Description Specifications AD5380-5 Specifications AD5380-3 Specifications AC Characteristics Timing Characteristics Serial Interface I2C Serial Interface Parallel Interface Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Terminology Typical Performance Characteristics Functional Description DAC Architecture—General Data Decoding On-Chip Special Function Registers (SFR) SFR Commands NOP (No Operation) Write CLR Code Soft CLR Soft Power-Down Soft Power-Up Soft RESET Control Register Write/Read Control Register Contents Channel Monitor Function Hardware Functions RESET\ Function Asynchronous Clear Function BUSY\ and LDAC\ Functions FIFO Operation in Parallel Mode Power-On Reset Power-Down AD5380 Interfaces DSP-, SPI-, Microwire-Compatible Serial Interfaces Standalone Mode Daisy-Chain Mode Readback Mode I2C Serial Interface I2C Data Transfer START and STOP Conditions Repeated START Conditions Acknowledge Bit (ACK) AD5380 Slave Addresses Write Operation 4-Byte Mode 3-Byte Mode 2-Byte Mode Parallel Interface CS\ Pin WR\ Pin REG0, REG1 Pins Pins A5 to A0 Pins DB13 to DB0 Microprocessor Interfacing Parallel Interface AD5380 to MC68HC11 AD5380 to PIC16C6x/7x AD5380 to 8051 AD5380 to ADSP-BF527 Applications Information Power Supply Decoupling Power Supply Sequencing Typical Configuration Circuit AD5380 Monitor Function Toggle Mode Function Thermal Monitor Function AD5380 in a MEMS Based Optical Switch Optical Attenuators Utilizing the AD5380 FIFO Outline Dimensions Ordering Guide