Datasheet AD5380 (Analog Devices) - 4

Data Sheet AD5380 REVISION HISTORY 5/14—Rev. C to Rev. D 9/12—Rev. B to Rev. C
Deleted ADSP-2103 .. Throughout Changes to Product Title.. 1 Changed ADSP-2101 to ADSP-BF527 ... Throughout Changes to General Description Section and Table 1 .. 3 Deleted Table 1; Renumbered Sequential y ... 3 Deleted Table 2; Renumbered Sequential y ... 3 Changes to General Description Section ... 4 Changed Logic Inputs (Except SDA/SCL), Input Current
6/12—Rev. A to Rev. B
Parameter, Table 1 from ±10 µA max to ±1 µA max .. 5 Changes to Features .. 1 Changed Logic Inputs (Except SDA/SCL), Input Current Changes to Table 3 .. 4 Parameter, Table 2 from ±10 µA max to ±1 µA max .. 7 Changes to Table 4 .. 6 Changes to Table 4 .. 9 Changes to Output Voltage Settling Time and Slew Rate Changes to Table 6 .. 12 Parameters, Table 5 ... 7 Changes to Soft Reset Section ... 23 Changes to t14 and t19 Parameters, Table 6 ... 8 Changes to Reset Function Section .. 26 Changes to Table 9 .. 13 Changes to Figure 38 .. 33 Changes to Figure 10, Figure 11, and Figure 14 ... 18 Added Power Supply Sequencing Section, Table 18, Figure 39, Changes to Figure 16, Figure 17, Figure 18, Figure 20... 19 and Figure 40; Renumbered Sequential y .. 34 Update Outline Dimensions and Changes to Ordering Guide .. . 38 Changed ADR280 to ADR3412, Typical Configuration Circuit Section .. 35
6/05—Rev. 0 to Rev. A
Added Figure 41 and Figure 42 ... 35 Changes to Specifications... 3 Changes to Terminology .. 17 Changes to Table 18 .. 24 Changes to Figure 43 .. 35
5/04—Revision 0: Initial Version
Rev. D | Page 3 of 40 Document Outline Features Integrated Functions Applications Functional Block Diagram Table Of Contents Revision History General Description Specifications AD5380-5 Specifications AD5380-3 Specifications AC Characteristics Timing Characteristics Serial Interface I2C Serial Interface Parallel Interface Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Terminology Typical Performance Characteristics Functional Description DAC Architecture—General Data Decoding On-Chip Special Function Registers (SFR) SFR Commands NOP (No Operation) Write CLR Code Soft CLR Soft Power-Down Soft Power-Up Soft RESET Control Register Write/Read Control Register Contents Channel Monitor Function Hardware Functions RESET\ Function Asynchronous Clear Function BUSY\ and LDAC\ Functions FIFO Operation in Parallel Mode Power-On Reset Power-Down AD5380 Interfaces DSP-, SPI-, Microwire-Compatible Serial Interfaces Standalone Mode Daisy-Chain Mode Readback Mode I2C Serial Interface I2C Data Transfer START and STOP Conditions Repeated START Conditions Acknowledge Bit (ACK) AD5380 Slave Addresses Write Operation 4-Byte Mode 3-Byte Mode 2-Byte Mode Parallel Interface CS\ Pin WR\ Pin REG0, REG1 Pins Pins A5 to A0 Pins DB13 to DB0 Microprocessor Interfacing Parallel Interface AD5380 to MC68HC11 AD5380 to PIC16C6x/7x AD5380 to 8051 AD5380 to ADSP-BF527 Applications Information Power Supply Decoupling Power Supply Sequencing Typical Configuration Circuit AD5380 Monitor Function Toggle Mode Function Thermal Monitor Function AD5380 in a MEMS Based Optical Switch Optical Attenuators Utilizing the AD5380 FIFO Outline Dimensions Ordering Guide