Datasheet AD5381 (Analog Devices)

40-Channel, 3 V/5 V, Single-Supply, 12-Bit, dense DAC Data Sheet AD5381 FEATURES INTEGRATED FUNCTIONS Guaranteed monotonic Channel monitor INL error: ±1 LSB max Simultaneous output update via LDAC On-chip 1.25 V/2.5 V, 10 ppm/°C reference Clear function to user-programmable code Temperature range: –40°C to +85°C Amplifier boost mode to optimize slew rate Rail-to-rail output amplifier User-programmable offset and gain adjust Power-down Toggle mode enables square wave generation Package type: 100-lead LQFP (14 mm × 14 mm) Thermal monitors User interfaces APPLICATIONS Parallel Serial (SPI®-/QSPI™-/MICROWIRE™-/DSP-compatible, Variable optical attenuators (VOAs) featuring data readback) Level setting (ATE) I2C®-compatible Optical micro-electro-mechanical systems (MEMs) Robust 6.5 kV HBM and 2 kV FICDM ESD rating Control systems Instrumentation FUNCTIONAL BLOCK DIAGRAM DVDD (×3) DGND (×3) AVDD (×5) AGND (×5) DAC_GND (×5) REFGND REFOUT/REFIN SIGNAL_GND (×5) PD AD5381 1.25V/2.5V SER/PAR REFERENCE FIFO EN CS/(SYNC/AD0) WR/(DCEN/AD1) 12 12 12 12 INPUT DAC SDO DAC 0 REG0 REG0 VOUT0 DB11/(DIN/SDA) 12 m REG0 DB10/(SCLK/SCL) FIFO 12 DB9/(SPI/I2C) c REG0 R + DB8 R INTERFACE STATE CONTROL MACHINE 12 12 12 12 LOGIC + INPUT DAC DAC 1 DB0 CONTROL REG1 REG1 VOUT1 LOGIC A5 12 VOUT2 m REG1 A0 12 c REG1 R VOUT3 R REG0 VOUT4 12 12 12 12 INPUT DAC VOUT5 REG1 DAC 6 REG6 REG6 POWER-ON VOUT6 RESET RESET 12 m REG6 BUSY 12 c REG6 R R CLR 12 12 12 12 INPUT DAC VOUT0………VOUT38 DAC 7 REG7 REG7 VOUT7 12 VOUT8 m REG7 39-TO-1 12 MUX c REG7 R R ×5 VOUT38
001 732-
VOUT39/MON_OUT LDAC
03 Figure 1.
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Document Outline Features Integrated Functions Applications Functional Block Diagram Table Of Contents Revision History General Description Specifications AD5381-5 Specifications AD5381-3 Specifications AC Characteristics Timing Characteristics Serial Interface Timing I2C Serial Interface Timing Parallel Interface Timing Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Terminology Typical Performance Characteristics Functional Description DAC Architecture—General Data Decoding On-Chip Special Function Registers (SFR) SFR Commands NOP (No Operation) Write CLR Code Soft CLR Soft Power-Down Soft Power-Up Soft RESET Control Register Write/Read Control Register Contents Channel Monitor Function Hardware Functions Reset Function Asynchronous Clear Function BUSY\ and LDAC\ Functions FIFO Operation in Parallel Mode Power-On Reset Power-Down Interfaces DSP-, SPI-, MICROWIRE-Compatible Serial Interfaces Standalone Mode Daisy-Chain Mode Readback Mode I2C Serial Interface I2C Data Transfer START and STOP Conditions Repeated START Conditions Acknowledge Bit (ACK) AD5381 Slave Addresses Write Operation 4-Byte Mode 3-Byte Mode 2-Byte Mode Parallel Interface CS\ Pin WR\ Pin REG0, REG1 Pins Pin A5 to Pin A0 Pin DB11 to Pin DB0 Microprocessor Interfacing Parallel Interface AD5381 to MC68HC11 AD5381 to PIC16C6x/7x AD5381 to 8051 AD5381 to ADSP-BF527 Applications Information Power Supply Decoupling Power Supply Sequencing Typical Configuration Circuit Monitor Function Toggle Mode Function Thermal Monitor Function Optical Attenuators Utilizing FIFO Outline Dimensions Ordering Guide