Datasheet AD5686, AD5684 (Analog Devices) - 9
| Hersteller | Analog Devices |
| Beschreibung | Quad, 16-/12-Bit nanoDAC+ with SPI Interface |
| Seiten / Seite | 27 / 9 — Data Sheet. AD5686/AD5684. ABSOLUTE MAXIMUM RATINGS. Table 6. Parameter … |
| Revision | C |
| Dateiformat / Größe | PDF / 757 Kb |
| Dokumentensprache | Englisch |
Data Sheet. AD5686/AD5684. ABSOLUTE MAXIMUM RATINGS. Table 6. Parameter Rating. ESD CAUTION
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Data Sheet AD5686/AD5684 ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted. Stresses at or above those listed under Absolute Maximum
Table 6.
Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these
Parameter Rating
or any other conditions above those indicated in the operational VDD to GND −0.3 V to +7 V section of this specification is not implied. Operation beyond VLOGIC to GND −0.3 V to +7 V the maximum operating conditions for extended periods may VOUT to GND −0.3 V to VDD + 0.3 V affect product reliability. VREF to GND −0.3 V to VDD + 0.3 V Digital Input Voltage to GND −0.3 V to VLOGIC + 0.3 V
ESD CAUTION
Operating Temperature Range −40°C to +105°C Storage Temperature Range −65°C to +150°C Junction Temperature 125°C 16-Lead TSSOP, θJA Thermal 112.6°C/W Impedance, 0 Airflow (4-Layer Board) 16-Lead LFCSP, θJA Thermal 70°C/W Impedance, 0 Airflow (4-Layer Board) Reflow Soldering Peak 260°C Temperature, Pb Free (J-STD-020) Rev. C | Page 9 of 27 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS AC CHARACTERISTICS TIMING CHARACTERISTICS DAISY-CHAIN AND READBACK TIMING CHARACTERISTICS Circuit and Timing Diagrams ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION DIGITAL-TO-ANALOG CONVERTER TRANSFER FUNCTION DAC ARCHITECTURE Output Amplifiers SERIAL INTERFACE Input Shift Register STANDALONE OPERATION WRITE AND UPDATE COMMANDS Write to Input Register n (Dependent on LDACB) Update DAC Register n with Contents of Input Register n Write to and Update DAC Channel n (Independent of LDACB) DAISY-CHAIN OPERATION READBACK OPERATION POWER-DOWN OPERATION LOAD DAC (HARDWARE LDACB PIN) Instantaneous DAC Updating (LDACB Held Low) Deferred DAC Updating (LDACB Is Pulsed Low) LDACB MASK REGISTER HARDWARE RESET (RESETB) RESET SELECT PIN (RSTSEL) APPLICATIONS INFORMATION MICROPROCESSOR INTERFACING AD5686/AD5684 TO ADSP-BF531 INTERFACE AD5686/AD5684 TO SPORT INTERFACE LAYOUT GUIDELINES GALVANICALLY ISOLATED INTERFACE OUTLINE DIMENSIONS ORDERING GUIDE
TA = 25°C, unless otherwise noted. Stresses at or above those listed under Absolute Maximum
Table 6.
Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these
Parameter Rating
or any other conditions above those indicated in the operational VDD to GND −0.3 V to +7 V section of this specification is not implied. Operation beyond VLOGIC to GND −0.3 V to +7 V the maximum operating conditions for extended periods may VOUT to GND −0.3 V to VDD + 0.3 V affect product reliability. VREF to GND −0.3 V to VDD + 0.3 V Digital Input Voltage to GND −0.3 V to VLOGIC + 0.3 V
ESD CAUTION
Operating Temperature Range −40°C to +105°C Storage Temperature Range −65°C to +150°C Junction Temperature 125°C 16-Lead TSSOP, θJA Thermal 112.6°C/W Impedance, 0 Airflow (4-Layer Board) 16-Lead LFCSP, θJA Thermal 70°C/W Impedance, 0 Airflow (4-Layer Board) Reflow Soldering Peak 260°C Temperature, Pb Free (J-STD-020) Rev. C | Page 9 of 27 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS AC CHARACTERISTICS TIMING CHARACTERISTICS DAISY-CHAIN AND READBACK TIMING CHARACTERISTICS Circuit and Timing Diagrams ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION DIGITAL-TO-ANALOG CONVERTER TRANSFER FUNCTION DAC ARCHITECTURE Output Amplifiers SERIAL INTERFACE Input Shift Register STANDALONE OPERATION WRITE AND UPDATE COMMANDS Write to Input Register n (Dependent on LDACB) Update DAC Register n with Contents of Input Register n Write to and Update DAC Channel n (Independent of LDACB) DAISY-CHAIN OPERATION READBACK OPERATION POWER-DOWN OPERATION LOAD DAC (HARDWARE LDACB PIN) Instantaneous DAC Updating (LDACB Held Low) Deferred DAC Updating (LDACB Is Pulsed Low) LDACB MASK REGISTER HARDWARE RESET (RESETB) RESET SELECT PIN (RSTSEL) APPLICATIONS INFORMATION MICROPROCESSOR INTERFACING AD5686/AD5684 TO ADSP-BF531 INTERFACE AD5686/AD5684 TO SPORT INTERFACE LAYOUT GUIDELINES GALVANICALLY ISOLATED INTERFACE OUTLINE DIMENSIONS ORDERING GUIDE