Datasheet AD7874 (Analog Devices) - 8

AD7874 OUTPUT
Gain error can be adjusted at either the first code transition
CODE
(ADC negative full scale) or the last code transition (ADC posi- tive full scale). The trim procedures for both cases are as
011...111
follows:
011...110 Positive Full-Scale Adjust
Apply a voltage of +9.9927 V (FS/2 – 3/2 LSBs) at V1. Adjust
000...010
R2 until the ADC output code flickers between 0111 1111 1110
000...001 – FS
and 0111 1111 1111.
2 000...000 Negative Full-Scale Adjust + FS 111...111 – 1LSB 2
Apply a voltage of –9.9976 V ( –FS + 1/2 LSB) at V1 and adjust
111...110
R2 until the ADC output code flickers between 1000 0000 0000
FS=20V
and 1000 0000 0001.
FS 1LSB = 4096 100...001
An alternative scheme for adjusting full-scale error in systems
100...000
which use an external reference is to adjust the voltage at the REF IN pin until the full-scale error for any of the channels is
0V
adjusted out. The good full-scale matching of the channels will
INPUT VOLTAGE
ensure small full-scale errors on the other channels. Figure 5. Input/Output Transfer Function
TIMING AND CONTROL
Conversion is initiated on the AD7874 by asserting the
OFFSET AND FULL-SCALE ADJUSTMENT
CONVST input. This CONVST input is an asynchronous input In most Digital Signal Processing (DSP) applications, offset and which is independent of the ADC clock. This is essential for full-scale errors have little or no effect on system performance. applications where precise sampling in time is important. In Offset error can always be eliminated in the analog domain by these applications, the signal sampling must occur at exactly ac coupling. Full-scale error effect is linear and does not cause equal intervals to minimize errors due to sampling uncertainty problems as long as the input signal is within the full dynamic or jitter. In these cases, the CONVST input is driven from a range of the ADC. Invariably, some applications will require timer or precise clock source. Once conversion is started, that the input signal span the full analog input dynamic range. CONVST should not be asserted again until conversion is com- In such applications, offset and full-scale error will have to be plete on all four channels. adjusted to zero. In applications where precise time interval sampling is not criti- Figure 6 shows a circuit which can be used to adjust the offset cal, the CONVST pulse can be generated from a microproces- and full-scale errors on the AD7874 (Channel 1 is shown for ex- sor WRITE or READ line gated with a decoded address ample purposes only). Where adjustment is required, offset er- (different to the AD7874 CS address). CONVST should not be ror must be adjusted before full-scale error. This is achieved by derived from a decoded address alone because very short trimming the offset of the op amp driving the analog input of CONVST pulses (which may occur in some microprocessor sys- the AD7874 while the input voltage is a 1/2 LSB below analog tems as the address bus is changing at the start of an instruction ground. The trim procedure is as follows: apply a voltage of cycle) could initiate a conversion. –2.44 mV (–1/2 LSB) at V1 in Figure 6 and adjust the op amp offset voltage until the ADC output code flickers between 1111 All four track/hold amplifiers go from track to hold on the rising 1111 1111 and 0000 0000 0000. edge of the CONVST pulse. The four track/hold amplifiers re- main in their hold mode while all four channels are converted.
INPUT
The rising edge of CONVST also initiates a conversion on the
RANGE =
±
10V
Channel 1 input voltage (V
V
IN1). When conversion is complete
1
on Channel 1, its result is stored in Data Register 1, one of four
R1
on-chip registers used to store the conversion results. When the
10k
Ω result from the first conversion is stored, conversion is initiated
R2
on the voltage held by track/hold 2. When conversion has been
500
Ω
VIN1
completed on the voltage held by track/hold 4 and its result is
R4
stored in Data Register 4, INT goes low to indicate that the
10k
Ω
AD7874*
conversion process is complete.
R3 R5 10k
Ω
10k
Ω The sequence in which the channel conversions takes place is
AGND
automatically taken care of by the AD7874. This means that the user does not have to provide address lines to the AD7874 or worry about selecting which channel is to be digitized. Reading data from the device consists of four read operations to
*ADDITIONAL PINS OMITTED FOR CLARITY
the same microprocessor address. Addressing of the four Figure 6. AD7874 Full-Scale Adjust Circuit on-chip data registers is again automatically taken care of by the AD7874. REV. C –7–