Datasheet AD7701 (Analog Devices) - 4

AD7701 Parameter A, S Version2 B, T Version2 Unit Test Conditions/Comments
POWER REQUIREMENTS8 Power Supply Voltages Analog Positive Supply (AVDD) 4.5/5.5 4.5/5.5 V min/V max Digital Positive Supply (DVDD) 4.5/AVDD 4.5/AVDD V min/V max Analog Negative Supply (AVSS) –4.5/–5.5 –4.5/–5.5 V min/V max Digital Negative Supply (DVSS) –4.5/–5.5 –4.5/–5.5 V min/V max Calibration Memory Retention Power Supply Voltage 2.0 2.0 V min DC Power Supply Currents8 Analog Positive Supply (AIDD) 2.7 2.7 mA max Typically 2 mA Digital Positive Supply (DIDD) 2 2 mA max Typically 1 mA Analog Negative Supply (AISS) 2.7 2.7 mA max Typically 2 mA Digital Negative Supply (DISS) 0.1 0.1 mA max Typically 0.03 mA Power Supply Rejection9 Positive Supplies 70 70 dB typ Negative Supplies 75 75 dB typ Power Dissipation Normal Operation 37 37 mW max SLEEP = Logic 1, Typically 25 mW Standby Operation10 20 (40 S Version) 20 (40 T Version) µW max SLEEP = Logic 0, Typically 10 µW NOTES 1The AIN pin presents a very high impedance dynamic load that varies with clock frequency. 2Temperature ranges are as follows: A, B Versions: –40°C to +85°C; S, T Versions: –55°C to +125°C. 3Apply after calibration at the temperature of interest. Full-scale error applies for both unipolar and bipolar input ranges. 4Total drift over the specified temperature range since calibration at power-up at 25 °C. This is guaranteed by design and/or characterization. Recalibration at any temperature will remove these errors. 5In Unipolar mode, the offset can have a negative value (–VREF) such that the Unipolar mode can mimic Bipolar mode operation. 6The specifications for input overrange and for input span apply additional constraints on the offset calibration range. 7For Unipolar mode, input span is the difference between full scale and zero scale. For Bipolar mode, input span is the difference between positive and negative full-scale points. When using less than the maximum input span, the span range may be placed anywhere within the range of ± (VREF +0.1). 8All digital outputs unloaded. All digital inputs at 5 V CMOS levels. 9Applies in 0.1 Hz to 10 Hz bandwidth. PSRR at 60 Hz will exceed 120 dB due to the digital filter. 10CLKIN is stopped. All digital inputs are grounded. Specifications subject to change without notice. REV. E –3– Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ORDERING GUIDE PIN CONFIGURATIONS PIN FUNCTION DESCRIPTIONS TIMING CHARACTERISTICS DEFINITION OF TERMS Linearity Error Differential Linearity Error Positive Full-Scale Error Unipolar Offset Error Bipolar Zero Error Bipolar Negative Full-Scale Error Positive Full-Scale Overrange Negative Full-Scale Overrange Offset Calibration Range Full-Scale Calibration Range Input Span GENERAL DESCRIPTION THEORY OF OPERATION DIGITAL FILTERING FILTER CHARACTERISTICS USING THE AD7701 SYSTEM DESIGN CONSIDERATIONS CLOCKING ANALOG INPUT RANGES INPUT SIGNAL CONDITIONING Source Resistance Antialias Considerations VOLTAGE REFERENCE CONNECTIONS GROUNDING AND SUPPLY DECOUPLING ACCURACY AND AUTOCALIBRATION CALIBRATION RANGE POWER-UP AND CALIBRATION POWER SUPPLY SEQUENCING GROUNDING SINGLE-SUPPLY OPERATION SLEEP MODE DIGITAL INTERFACE Synchronous Self-Clocking Mode (SSC) Synchronous External Clock Mode (SEC) Asynchronous Communications (AC) Mode DIGITAL NOISE AND OUTPUT LOADING OUTLINE DIMENSIONS Revision History