Datasheet AD7880 (Analog Devices) - 10

AD7880 MICROPROCESSOR INTERFACING TIMER
The AD7880 high speed bus timing allows direct interfacing to
PA2
real time digital signal processors, DSPs, as well as modern high
ADDRESS BUS
speed, 16-bit microprocessors. Suitable microprocessor inter-
PA0
faces are shown in Figures 15 through 20.
ADDR AD7880–ADSP-2100 Interface CONVST DECODE
Figure 15 shows an interface between the AD7880 and the
MEN CS EN
ADSP-2100. Conversion is initiated using a timer to drive the CONVST input asynchronously to the microprocessor. This al-
TMS32010 AD7880*
lows very accurate control of the sampling instant. When con- version is complete, the AD7880 BUSY line goes high. An
DEN RD
inverter on this BUSY output drives the IRQ line low thus pro- viding an interrupt to the ADSP-2100 when conversion is com-
INT BUSY
pleted. The conversion result is then read from the AD7880 into
DB11
A the ADSP-2100 with the following instruction:
DB0
A MR0 = DM(ADC)
D15
where MR0 is the ADSP-2100 MR0 Register and
DATA BUS D0
where ADC is the AD7880 address.
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 16. AD7880–TMS32010 Interface
DMA13 TIMER AD7880–TMS320C25 Interface ADDRESS BUS DMA0
Figure 17 shows an interface between the AD7880 and the TMS320C25. As with the two previous interfaces, conversion is
CONVST ADDR
initiated with a timer, and the processor is interrupted when the
DECODE CS
conversion sequence is completed. The TMS320C25 does not
DMS EN
have a separate RD output to drive the AD7880 RD input di- rectly. This has to be generated from the processor STRB and
ADSP-2100 AD7880* (ADSP-2101/
R/W outputs with the addition of some logic gates. The RD sig-
ADSP-2102)
nal is OR-gated with the MSC signal to provide the one WAIT state required in the read cycle for correct interface timing.
DMRD (RD) RD
Conversion results are read from the AD7880 using the follow- ing instruction:
IRQn BUSY
IN D,ADC
DB11
A where D is Data Memory Address and
DB0
A where ADC is the AD7880 address.
DMD15 DATA BUS TIMER DMD0 * ADDITIONAL PINS OMITTED FOR CLARITY A15 ADDRESS BUS A0
Figure 15. AD7880–ADSP-2100 (ADSP-2101/ADSP-2102) Interface
ADDR CONVST DECODE AD7880-ADSP-2101/ADSP-2102 Interface IS EN CS
The interface outlined in Figure 15 also forms the basis for an
TMS320C25 AD7880*
interface between the AD7880 and the ADSP-2101/ADSP-2102. The READ line of the ADSP-2101/ADSP-2102 is labeled RD.
INTn BUSY
In this interface, the RD pulse width of the processor can be
STRB
programmed using the Data Memory Wait State Control Regis-
RD R/W
ter. The instruction used to read a conversion result is as out- lined for the ADSP-2100.
READY DB11 AD7880-TMS32010 Interface
A
MSC DB0
An interface between the AD7880 and the TMS32010 is shown A in Figure 16. Once again the conversion is initiated using an ex-
D15
ternal timer and the TMS32010 is interrupted when conversion
DATA BUS D0
is completed. The following instruction is used to read the con-
*ADDITIONAL PINS OMITTED FOR CLARITY
version result from the AD7880: Figure 17. AD7880–TMS320C25 Interface IN D,ADC Some applications may require that the conversion be initiated where D is Data Memory Address and by the microprocessor rather than an external timer. One option where ADC is the AD7880 address. is to decode the AD7880 CONVST from the address bus so that REV. 0 –9–