Datasheet AD1674 (Analog Devices) - 6

AD1674 (for all grades TMIN to TMAX with VCC = +15 V
6
10% or +12 V
6
5%, VLOGIC = +5 V
6
10%, VEE = –15 V
6
10% or –12 V
6
5%; VIL = 0.4 V, VIH = 2.4 V unless otherwise noted) SWITCHING SPECIFICATIONS CONVERTER START TIMING (Figure 1) J, K, A, B, Grades T Grade Parameter Symbol Min Typ Max Min Typ Max Units tHEC CE
Conversion Time
__ t
8-Bit Cycle t
CS HSC
C 7 8 7 8 µs
tSSC
12-Bit Cycle tC 9 10 9 10 µs STS Delay from CE tDSC 200 225 ns
_ t t SRC HRC
CE Pulse Width t
R/C
HEC 50 50 ns CS to CE Setup tSSC 50 50 ns CS Low During CE High tHSC 50 50 ns R/C to CE Setup tSRC 50 50 ns
A t 0 SAC tHAC
R/C Low During CE High tHRC 50 50 ns A
t
0 to CE Setup tSAC 0 0 ns
C
A0 Valid During CE High tHAC 50 50 ns
STS tDSC DB11 – DB0 HIGH IMPEDANCE READ TIMING—FULL CONTROL MODE (Figure 2) J, K, A, B, Grades T Grade
Figure 1. Converter Start Timing
Parameter Symbol Min Typ Max Min Typ Max Units
Access Time t 1 DD 75 150 75 150 ns Data Valid After CE Low tHD 252 252 ns
CE __
203 154 ns
CS
Output Float Delay t 5
t t
HL 150 150 ns
HSR SSR
CS to CE Setup tSSR 50 50 ns R/C to CE Setup tSRR 0 0 ns
_
A0 to CE Setup tSAR 50 50 ns
R/C t t SSR HRR
CS Valid After CE Low tHSR 0 0 ns R/C High After CE Low tHRR 0 0 ns A0 Valid After CE Low tHAR 50 50 ns
A0 tSAR tHAR
NOTES 1tDD is measured with the load circuit of Figure 3 and is defined as the time required for an output to cross 0.4 V or 2.4 V.
tHS
20°C to T
STS
MAX. 3At –40°C.
t
4
HD
At –55°C. 5t
HIGH DATA HIGH
HL is defined as the time required for the data lines to change 0.5 V when
DB11 – DB0
loaded with the circuit of Figure 3.
IMPEDANCE VALID IMP.
All min and max specifications are guaranteed.
t t DD HL
Specifications subject to change without notice. Figure 2. Read Timing
Test VCP COUT
Access Time High Z to Logic Low 5 V 100 pF
IOL
Float Time Logic High to High Z 0 V 10 pF Access Time High Z to Logic High 0 V 100 pF Float Time Logic Low to High Z 5 V 10 pF
DOUT VCP COUT IOH
Figure 3. Load Circuit for Bus Timing Specifications REV. C –5–