Datasheet AD7710 (Analog Devices) - 10

AD7710 CONTROL REGISTER (24 BITS)
A write to the device with the A0 input low writes data to the control register. A read to the device with the A0 input low accesses the contents of the control register. The control register is 24 bits wide; 24 bits of data must be written to the register or the data will not be loaded. In other words, it is not possible to write just the first 12 bits of data into the control register. If more than 24 clock pulses are provided before TFS returns high, then all clock pulses after the 24th clock pulse are ignored. Similarly, a read operation from the control register should access 24 bits of data.
MSB MD2 MD1 MD0 G2 G1 G0 CH PD WL IO BO B/U FS11 FS10 FS9 FS8 FS7 FS6 FS5 FS4 FS3 FS2 FS1 FS0 LSB Operating Mode MD2 MD1 MD0 Operating Mode
0 0 0 Normal Mode. This is the normal mode where a read to the device with A0 high accesses data from the data register. This is the default condition of these bits after the internal power-on reset. 0 0 1 Activate Self-Calibration. This activates self-calibration on the channel selected by CH. This is a one-step calibration sequence, and when complete, the part returns to normal mode (with MD2, MD1, MD0 of the control register returning to 0, 0, 0). The DRDY output indicates when this self-calibration is complete. For this calibration type, the zero-scale calibration is done internally on shorted (zeroed) inputs, and the full-scale calibration is done internally on VREF. 0 1 0 Activate System Calibration. This activates system calibration on the channel selected by CH. This is a two-step calibration sequence, with the zero-scale calibration done first on the selected input channel and DRDY indicating when this zero-scale calibration is complete. The part returns to normal mode at the end of this first step in the two-step sequence. 0 1 1 Activate System Calibration. This is the second step of the system calibration sequence with full-scale calibration being performed on the selected input channel. Once again, DRDY indicates when the full- scale calibration is complete. When this calibration is complete, the part returns to normal mode. 1 0 0 Activate System Offset Calibration. This activates system offset calibration on the channel selected by CH. This is a one-step calibration sequence and, when complete, the part returns to normal mode with DRDY indicating when this system offset calibration is complete. For this calibration type, the zero-scale calibration is done on the selected input channel, and the full-scale calibration is done internally on VREF. 1 0 1 Activate Background Calibration. This activates background calibration on the channel selected by CH. If the background calibration mode is on, then the AD7710 provides continuous self-calibration of the reference and shorted (zeroed) inputs. This calibration takes place as part of the conversion sequence, extending the conversion time and reducing the word rate by a factor of 6. The major advantage of using this mode is that the user does not have to recalibrate the device when there is a change in the ambient temperature. In this mode, the shorted (zeroed) inputs and VREF, as well as the analog input voltage, are continuously monitored and the calibration registers of the device are automatically updated. 1 1 0 Read/Write Zero-Scale Calibration Coefficients. A read to the device with A0 high accesses the contents of the zero-scale calibration coefficients of the channel selected by CH. A write to the device with A0 high writes data to the zero-scale calibration coefficients of the channel selected by CH. The word length for reading and writing these coefficients is 24 bits, regardless of the status of the WL bit of the control register. Therefore, 24 bits of data must be written to the calibration register, or the new data will not be transferred to the calibration register. 1 1 1 Read/Write Full-Scale Calibration Coefficients. A read to the device with A0 high accesses the contents of the full-scale calibration coefficients of the channel selected by CH. A write to the device with A0 high writes data to the full-scale calibration coefficients of the channel selected by CH. The word length for reading and writing these coefficients is 24 bits, regardless of the status of the WL bit of the control register. Therefore, 24 bits of data must be written to the calibration register, or the new data will not be transferred to the calibration register. REV. G –9– Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS TIMING CHARACTERISTICS ORDERING GUIDE PIN CONFIGURATION PIN FUNCTION DESCRIPTIONS Terminology Integral Nonlinearity Positive Full-Scale Error Unipolar Offset Error Bipolar Zero Error Bipolar Negative Full-Scale Error Positive Full-Scale Overrange Negative Full-Scale Overrange Offset Calibration Range Full-Scale Calibration Range Input Span CONTROL REGISTER (24 BITS) PGA GAIN CHANNEL SELECTION Power-Down Word Length Output Compensation Current Burn-Out Current Bipolar/Unipolar Selection (Both Inputs) FILTER SELECTION (FS11–FS0) CIRCUIT DESCRIPTION THEORY OF OPERATION Input Sample Rate DIGITAL FILTERING Filter Characteristics Post Filtering Antialias Considerations ANALOG INPUT FUNCTIONS Analog Input Ranges Burnout Current Output Compensation Current Bipolar/Unipolar Inputs REFERENCE INPUT/OUTPUT VBIAS Input USING THE AD7710 SYSTEM DESIGN CONSIDERATIONS Clocking System Synchronization Accuracy Autocalibration Self-Calibration System Calibration System Offset Calibration Background Calibration Span and Offset Limits POWER-UP AND CALIBRATION Drift Considerations POWER SUPPLIES AND GROUNDING DIGITAL INTERFACE Self-Clocking Mode Read Operation Write Operation External Clocking Mode Read Operation Write Operation SIMPLIFYING THE EXTERNAL CLOCKING MODE INTERFACE MICROCOMPUTER/MICROPROCESSOR INTERFACING AD7710 to 8XC51 Interface AD7710 to 68HC11 Interface APPLICATIONS OUTLINE DIMENSIONS Revision History