Datasheet AD7711 (Analog Devices) - 9

AD7711 Pin Mnemonic Function
20 RFS Receive Frame Synchronization. Active low logic input used to access serial data from the device. In the self-clocking mode, the SCLK and SDATA lines both become active after RFS goes low. In the external clocking mode, the SDATA line becomes active after RFS goes low. 21 DRDY Logic Output. A falling edge indicates that a new output word is available for transmission. The DRDY pin will return high upon completion of transmission of a full output word. DRDY is also used to indicate when the AD7711 has completed its on-chip calibration sequence. 22 SDATA Serial Data. Input/output with serial data being written to either the control register or the calibration registers and serial data being accessed from the control register, calibration registers, or the data register. During an output data read operation, serial data becomes active after RFS goes low (provided DRDY is low). During a write operation, valid serial data is expected on the rising edges of SCLK when TFS is low. The output data coding is natural binary for unipolar inputs and offset binary for bipolar inputs. 23 DVDD Digital Supply Voltage, 5 V. DVDD should not exceed AVDD by more than 0.3 V in normal operation. 24 DGND Ground Reference Point for Digital Circuitry.
TERMINOLOGY Positive Full-Scale Overrange Intergral Nonlinearity
Positive full-scale overrange is the amount of overhead avail- This is the maximum deviation of any code from a straight line able to handle input voltages on the AIN1(+) input greater passing through the endpoints of the transfer function. The end- than AIN1(–) + VREF/GAIN or on the AIN2 input greater points of the transfer function are zero-scale (not to be confused than + VREF/GAIN (for example, noise peaks or excess with bipolar zero), a point 0.5 LSB below the first code transi- voltages due to system gain errors in system calibration rou- tion (000 . 000 to 000 . 001) and full scale, a point 0.5 LSB tines) without introducing errors due to overloading the analog above the last code transition (111 . 110 to 111 . 111). The modulator or to overflowing the digital filter. error is expressed as a percentage of full scale.
Negative Full-Scale Overrange Positive Full-Scale Error
This is the amount of overhead available to handle voltages on Positive full-scale error is the deviation of the last code transi- AIN1(+) below AIN1(–) – VREF/GAIN or on AIN2 below tion (111 . 110 to 111 . 111) from the ideal input full-scale –VREF/GAIN without overloading the analog modulator or over- voltage. For AIN1(+), the ideal full-scale input voltage is flowing the digital filter. Note that the analog input will accept (AIN1(–) + VREF/GAIN – 3/2 LSBs); for AIN2, the ideal full- negative voltage peaks on AIN1(+) even in the unipolar mode scale input voltage is VREF/GAIN – 3/2 LSBs. It applies to both provided that AIN1(+) is greater than AIN1(–) and greater than unipolar and bipolar analog input ranges. VSS – 30 mV.
Unipolar Offset Error Offset Calibration Range
Unipolar offset error is the deviation of the first code transition In the system calibration modes, the AD7711 calibrates its from the ideal voltage. For AIN1(+), the ideal input voltage is offset with respect to the analog input. The offset calibration (AIN1(–) + 0.5 LSB); for AIN2, the ideal input is 0.5 LSB range specification defines the range of voltages that the AD7711 when operating in the unipolar mode. can accept and still calibrate offset accurately.
Bipolar Zero Error Full-Scale Calibration Range
This is the deviation of the midscale transition (0111 . 111 This is the range of voltages that the AD7711 can accept in the to 1000 . 000) from the ideal input voltage. For AIN1(+), the system calibration mode and still calibrate full-scale correctly. ideal input voltage is (AIN1(–) – 0.5 LSB); for AIN2, the ideal input is – 0.5 LSB when operating in the bipolar mode.
Input Span
In system calibration schemes, two voltages applied in sequence
Bipolar Negative Full-Scale Error
to the AD7711’s analog input define the analog input range. This is the deviation of the first code transition from the ideal The input span specification defines the minimum and maxi- input voltage. For (AIN1(+), the ideal input voltage is (AIN1(–) mum input voltages from zero- to full-scale that the AD7711 – VREF/GAIN + 0.5 LSB); for AIN2 the ideal input is – VREF/GAIN can accept and still calibrate gain accurately. + 0.5 LSB when operating in the bipolar mode. –8– REV. G Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS SPECIFICATIONS TIMING CHARACTERISTICS PIN FUNCTION DESCRIPTIONS TERMINOLOGY Intergral Nonlinearity Positive Full-Scale Error Unipolar Offset Error Bipolar Zero Error Bipolar Negative Full-Scale Error Positive Full-Scale Overrange Negative Full-Scale Overrange Offset Calibration Range Full-Scale Calibration Range Input Span CONTROL REGISTER (24 BITS) FILTER SELECTION (FS11–FS0) CIRCUIT DESCRIPTION THEORY OF OPERATION Input Sample Rate DIGITAL FILTERING Filter Characteristics Post Filtering Antialias Considerations ANALOG INPUT FUNCTIONS Analog Input Ranges Burnout Current RTD Excitation Current Bipolar/Unipolar Inputs REFERENCE INPUT/OUTPUT VBIAS Input USING THE AD7711 SYSTEM DESIGN CONSIDERATIONS Clocking System Synchronization Accuracy Autocalibration Self-Calibration System Calibration System Offset Calibration Background Calibration Span and Offset Limits POWER-UP AND CALIBRATION Drift Considerations POWER SUPPLIES AND GROUNDING DIGITAL INTERFACE Self-Clocking Mode Read Operation Write Operation External Clocking Mode Read Operation Write Operation SIMPLIFYING THE EXTERNAL CLOCKING MODE INTERFACE MICROCOMPUTER/MICROPROCESSOR INTERFACING AD7711 to 8051 Interface AD7711 to 68HC11 Interface APPLICATIONS 4-Wire RTD Configurations 3-Wire RTD Configurations OUTLINE DIMENSIONS Revision History