Datasheet AD7711 (Analog Devices) - 4

AD7711 Parameter A, S Versions1 Unit Conditions/Comments
VBIAS INPUT12 Input Voltage Range AVDD – 0.85 ¥ VREF See VBIAS Input Section or AVDD – 3.5 V max Whichever Is Smaller; +5 V/–5 V or +10 V/0 V Nominal AVDD/VSS or AVDD – 2.1 V max Whichever Is Smaller; +5 V/0 V Nominal AVDD/VSS VSS + 0.85 ¥ VREF See VBIAS Input Section or VSS + 3 V min Whichever Is Greater; +5 V/–5 V or +10 V/0 V Nominal AVDD/VSS or VSS + 2.1 V min Whichever Is Greater; +5 V/0 V Nominal AVDD/VSS VBIAS Rejection 65 to 85 dB typ Increasing with Gain LOGIC INPUTS Input Current ±10 mA max All Inputs except MCLK IN VINL, Input Low Voltage 0.8 V max VINH, Input High Voltage 2.0 V min MCLK IN Only VINL, Input Low Voltage 0.8 V max VINH, Input High Voltage 3.5 V min LOGIC OUTPUTS VOL, Output Low Voltage 0.4 V max ISINK = 1.6 mA VOH, Output High Voltage 4.0 V min ISOURCE = 100 mA Floating State Leakage Current ±10 mA max Floating State Output Capacitance13 9 pF typ TRANSDUCER BURNOUT Current 4.5 mA nom Initial Tolerance @ 25∞C ±10 % typ Drift 0.1 %/∞C typ RTD EXCITATION CURRENTS (RTD1, RTD2) Output Current 200 mA nom Initial Tolerance @ 25∞C ±20 % max Drift 20 ppm/∞C typ Initial Matching @ 25∞C ±1 % max Matching between RTD1 and RTD2 Currents Drift Matching 3 ppm/∞C typ Matching between RTD1 and RTD2 Current Drift Line Regulation (AVDD) 200 nA/V max AVDD = 5 V Load Regulation 200 nA/V max Output Compliance AVDD – 2 V max SYSTEM CALIBRATION Positive Full-Scale Calibration Limit14 (1.05 ¥ VREF)/GAIN V max GAIN Is the Selected PGA Gain (between 1 and 128) Negative Full-Scale Calibration Limit14 –(1.05 ¥ VREF)/GAIN V max GAIN Is the Selected PGA Gain (between 1 and 128) Offset Calibration Limit15 –(1.05 ¥ VREF)/GAIN V max GAIN Is the Selected PGA Gain (between 1 and 128) Input Span15 0.8 ¥ VREF/GAIN V min GAIN Is the Selected PGA Gain (between 1 and 128) (2.1 ¥ VREF)/GAIN V max GAIN Is the Selected PGA Gain (between 1 and 128) NOTES 12The AD7711 is tested with the following VBIAS voltages. With AVDD = 5 V and VSS = 0 V, VBIAS = 2.5 V; with AVDD = 10 V and VSS = 0 V, VBIAS = 5 V, and with AVDD = 5 V and VSS = –5 V, VBIAS = 0 V. 13Guaranteed by design, not production tested. 14After calibration, if the analog input exceeds positive full scale, the converter outputs all 1s. If the analog input is less than negative full scale, the device outputs all 0s. 15These calibration and span limits apply, provided the absolute voltage on the analog inputs does not exceed AVDD + 30 mV or go more negative than VSS – 30 mV. The offset calibration limit applies to both the unipolar zero point and the bipolar zero point. REV. G –3– Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS SPECIFICATIONS TIMING CHARACTERISTICS PIN FUNCTION DESCRIPTIONS TERMINOLOGY Intergral Nonlinearity Positive Full-Scale Error Unipolar Offset Error Bipolar Zero Error Bipolar Negative Full-Scale Error Positive Full-Scale Overrange Negative Full-Scale Overrange Offset Calibration Range Full-Scale Calibration Range Input Span CONTROL REGISTER (24 BITS) FILTER SELECTION (FS11–FS0) CIRCUIT DESCRIPTION THEORY OF OPERATION Input Sample Rate DIGITAL FILTERING Filter Characteristics Post Filtering Antialias Considerations ANALOG INPUT FUNCTIONS Analog Input Ranges Burnout Current RTD Excitation Current Bipolar/Unipolar Inputs REFERENCE INPUT/OUTPUT VBIAS Input USING THE AD7711 SYSTEM DESIGN CONSIDERATIONS Clocking System Synchronization Accuracy Autocalibration Self-Calibration System Calibration System Offset Calibration Background Calibration Span and Offset Limits POWER-UP AND CALIBRATION Drift Considerations POWER SUPPLIES AND GROUNDING DIGITAL INTERFACE Self-Clocking Mode Read Operation Write Operation External Clocking Mode Read Operation Write Operation SIMPLIFYING THE EXTERNAL CLOCKING MODE INTERFACE MICROCOMPUTER/MICROPROCESSOR INTERFACING AD7711 to 8051 Interface AD7711 to 68HC11 Interface APPLICATIONS 4-Wire RTD Configurations 3-Wire RTD Configurations OUTLINE DIMENSIONS Revision History