Datasheet AD7712 (Analog Devices) - 4

AD7712 SPECIFICATIONS (continued) Parameter A, S Versions1 Unit Conditions/Comments
REFERENCE OUTPUT Output Voltage 2.5 V nom Initial Tolerance ±1 % max Drift 20 ppm/°C typ Output Noise 30 µV typ pk-pk Noise; 0.1 Hz to 10 Hz Bandwidth Line Regulation (AVDD) 1 mV/V max Load Regulation 1.5 mV/mA max Maximum Load Current 1 mA External Current 1 mA max VBIAS INPUT13 Input Voltage Range AVDD – 0.85 ⫻ VREF See VBIAS Input Section or AVDD – 3.5 V max Whichever Is Smaller: +5 V/–5 V or +10 V/0 V Nominal AVDD/VSS or AVDD – 2.1 V max Whichever Is Smaller: +5 V/0 V Nominal AVDD/VSS VSS + 0.85 ⫻ VREF See VBIAS Input Section or VSS + 3 V min Whichever Is Greater: +5 V/–5 V or +10 V/0 V Nominal AVDD/VSS or VSS + 2.1 V min Whichever Is Greater: +5 V/0 V Nominal AVDD/VSS VBIAS Rejection 65 to 85 dB typ Increasing with Gain LOGIC INPUTS Input Current ±10 µA max All Inputs except MCLK IN VINL, Input Low Voltage 0.8 V max VINH, Input High Voltage 2.0 V min MCLK IN Only VINL, Input Low Voltage 0.8 V max VINH, Input High Voltage 3.5 V min LOGIC OUTPUTS VOL, Output Low Voltage 0.4 V max ISINK = 1.6 mA VOH, Output High Voltage 4.0 V min ISOURCE = 100 µA Floating State Leakage Current ±10 µA max Floating State Output Capacitance14 9 pF typ TRANSDUCER BURNOUT Current 4.5 µA nom Initial Tolerance ±10 % typ Drift 0.1 %/°C typ SYSTEM CALIBRATION AIN1 Positive Full-Scale Calibration Limit15 (1.05 ⫻ VREF)/GAIN V max GAIN Is the Selected PGA Gain (Between 1 and 128) Negative Full-Scale Calibration Limit15 –(1.05 ⫻ VREF)/GAIN V max GAIN Is the Selected PGA Gain (Between 1 and 128) Offset Calibration Limit16, 17 –(1.05 ⫻ VREF)/GAIN V max GAIN Is the Selected PGA Gain (Between 1 and 128) Input Span15 0.8 ⫻ VREF/GAIN V min GAIN Is the Selected PGA Gain (Between 1 and 128) (2.1 ⫻ VREF)/GAIN V max GAIN Is the Selected PGA Gain (Between 1 and 128) AIN2 Positive Full-Scale Calibration Limit15 (4.2 ⫻ VREF)/GAIN V max GAIN Is the Selected PGA Gain (Between 1 and 128) Negative Full-Scale Calibration Limit15 –(4.2 ⫻ VREF)/GAIN V max GAIN Is the Selected PGA Gain (Between 1 and 128) Offset Calibration Limit17 –(4.2 ⫻ VREF)/GAIN V max GAIN Is the Selected PGA Gain (Between 1 and 128) Input Span15 3.2 ⫻ VREF/GAIN V min GAIN Is the Selected PGA Gain (Between 1 and 128) (8.4 ⫻ VREF)/GAIN V max GAIN Is the Selected PGA Gain (Between 1 and 128) NOTES 13The AD7712 is tested with the following VBIAS voltages. With AVDD = 5 V and VSS = 0 V, VBIAS = 2.5 V; with AVDD = 10 V and VSS = 0 V, VBIAS = 5 V and with AVDD = 5 V and VSS = –5 V, VBIAS = 0 V. 14Guaranteed by design, not production tested. 15After calibration, if the analog input exceeds positive full scale, the converter will output all 1s. If the analog input is less than negative full scale, then the device will output all 0s. 16These calibration and span limits apply provided the absolute voltage on the AIN1 analog inputs does not exceed AV DD + 30 mV or does not go more negative than VSS – 30 mV. 17The offset calibration limit applies to both the unipolar zero point and the bipolar zero point. REV. F –3– Document Outline ANALOG INPUT FUNCTIONS FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ORDERING GUIDE TIMING CHARACTERISTICS PIN CONFIGURATION PIN FUNCTION DESCRIPTION TERMINOLOGY Integral Nonlinearity Positive Full-Scale Error Bipolar Zero Error Bipolar Negative Full-Scale Error Positive Full-Scale Overrange Negative Full-Scale Overrange Offset Calibration Range Full-Scale Calibration Range Input Span Control Register (24 Bits) Filter Selection (FS11–FS0) CIRCUIT DESCRIPTION THEORY OF OPERATION Input Sample Rate DIGITAL FILTERING Filter Characteristics Post Filtering Antialias Considerations ANALOG INPUT FUNCTIONS Analog Input Ranges Burnout Current Bipolar/Unipolar Inputs REFERENCE INPUT/OUTPUT VBIAS Input USING THE AD7712 SYSTEM DESIGN CONSIDERATIONS Clocking System Synchronization Accuracy Autocalibration Self-Calibration System Calibration System Offset Calibration Background Calibration Span and Offset Limits POWER-UP AND CALIBRATION Drift Considerations POWER SUPPLIES AND GROUNDING DIGITAL INTERFACE Self-Clocking Mode Read Operation Write Operation External Clocking Mode Read Operation Write Operation SIMPLIFYING THE EXTERNAL CLOCKING MODE INTERFACE MICROCOMPUTER/MICROPROCESSOR INTERFACING AD7712 to 8051 Interface AD7712 to 68HC11 Interface APPLICATIONS 4–20 mA LOOP OUTLINE DIMENSIONS Revision History