Datasheet AD7713 (Analog Devices) - 8

AD7713 PIN CONFIGURATION PDIP, CERDIP, AND SOIC SCLK 1 24 DGND MCLK IN 2 23 DVDD MCLK OUT 3 22 SDATA A0 4 21 DRDY SYNC 5 20 RFS AD7713 MODE 6 TOP VIEW 19 TFS (Not to Scale) AIN1(+) 7 18 AGND AIN1(–) 8 17 AIN3 AIN2(+) 9 16 RTD2 AIN2(–) 10 15 REF IN(+) STANDBY 11 14 REF IN(–) AV 12 DD 13 RTD1 PIN FUNCTION DESCRIPTION Pin No. Mnemonic Function
1 SCLK Serial Clock. Logic input/output, depending on the status of the MODE pin. When MODE is high, the device is in its self-clocking mode, and the SCLK pin provides a serial clock output. This SCLK be- comes active when RFS or TFS goes low, and it goes high impedance when either RFS or TFS returns high or when the device has completed transmission of an output word. When MODE is low, the device is in its external clocking mode and the SCLK pin acts as an input. This input serial clock can be a con- tinuous clock with all data transmitted in a continuous train of pulses. Alternatively, it can be a noncontinuous clock with the information being transmitted to the AD7713 in smaller batches of data. 2 MCLK IN Master Clock Signal for the Device. This can be provided in the form of a crystal or external clock. A crystal can be tied across the MCLK IN and MCLK OUT pins. Alternatively, the MCLK IN pin can be driven with a CMOS-compatible clock and MCLK OUT left unconnected. The clock input frequency is nominally 2 MHz. 3 MCLK OUT When the master clock for the device is a crystal, the crystal is connected between MCLK IN and MCLK OUT. 4 A0 Address Input. With this input low, reading and writing to the device is to the control register. With this input high, access is to either the data register or the calibration registers. 5 SYNC Logic Input. Allows for synchronization of the digital filters when using a number of AD7713s. It resets the nodes of the digital filter. 6 MODE Logic Input. When this pin is high, the device is in its self-clocking mode. With this pin low, the device is in its external clocking mode. 7 AIN1(+) Analog Input Channel 1. Positive input of the programmable gain differential analog input. The AIN1(+) input is connected to an output current source that can be used to check that an external transducer has burnt out or gone open circuit. This output current source can be turned on/off via the control register. 8 AIN1(–) Analog Input Channel 1. Negative input of the programmable gain differential analog input. 9 AIN2(+) Analog Input Channel 2. Positive input of the programmable gain differential analog input. 10 AIN2(–) Analog Input Channel 2. Negative input of the programmable gain differential analog input. 11 STANDBY Logic Input. Taking this pin low shuts down the internal analog and digital circuitry, reducing power consumption to less than 100 µW. 12 AVDD Analog Positive Supply Voltage, 5 V to 10 V. 13 RTD1 Constant Current Output. A nominal 200 µA constant current is provided at this pin, which can be used as the excitation current for RTDs. This current can be turned on or off via the control register. 14 REF IN(–) Reference Input. The REF IN(–) can lie anywhere between AVDD and AGND, provided REF IN(+) is greater than REF IN(–). 15 REF IN(+) Reference Input. The reference input is differential providing that REF IN(+) is greater than REF IN(–). REF IN(+) can lie anywhere between AVDD and AGND. REV. D –7– Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ORDERING GUIDE PIN CONFIGURATION PIN FUNCTION DESCRIPTION TERMINOLOGY Integral Nonlinearity Positive Full-Scale Error Unipolar Offset Error Bipolar Zero Error Bipolar Negative Full-Scale Error Positive Full-Scale Overrange Negative Full-Scale Overrange Offset Calibration Range Full-Scale Calibration Range Input Span CONTROL REGISTER (24 BITS) Filter Selection (FS11 to FS0) CIRCUIT DESCRIPTION THEORY OF OPERATION Input Sample Rate DIGITAL FILTERING Filter Characteristics Post Filtering Antialias Considerations ANALOG INPUT FUNCTIONS Analog Input Ranges Burn Out Current RTD Excitation Currents Bipolar/Unipolar Inputs REFERENCE INPUT USING THE AD7713 SYSTEM DESIGN CONSIDERATIONS Clocking System Synchronization Accuracy Autocalibration Self-Calibration System Calibration System Offset Calibration Background Calibration Span and Offset Limits POWER-UP AND CALIBRATION Drift Considerations POWER SUPPLIES AND GROUNDING DIGITAL INTERFACE Self-Clocking Mode Read Operation Write Operation External Clocking Mode Read Operation Write Operation SIMPLIFYING THE EXTERNAL CLOCKING MODE INTERFACE MICROCOMPUTER/MICROPROCESSOR INTERFACING AD7713 to 8XC51 Interface AD7713 to 68HC11 Interface APPLICATIONS 4-Wire RTD Configurations 3-Wire RTD Configurations 4–20 mA Loop OTHER 24-BIT SIGNAL CONDITIONING ADCS AVAILABLE FROM ANALOG DEVICES AD7710 AD7711 AD7712 OUTLINE DIMENSIONS Revision History