Datasheet AD7716 (Analog Devices)

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LC2MOS 22-Bit Data Acquisition System AD7716 FEATURES FUNCTIONAL BLOCK DIAGRAM 22-Bit Sigma-Delta ADC AV AV RESET CLKIN CLKOUT DD DVDD SS A0 A1 A2 Dynamic Range of 105 dB (146 Hz Input)
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0.003% Integral Nonlinearity AD7716 On-Chip Low-Pass Digital Filter CLOCK GENERATION Cutoff Programmable from 584 Hz to 36.5 Hz LOW PASS ANALOG A 1 IN DIGITAL MODULATOR Linear Phase Response FILTER MODE CONTROL CASCIN Five Line Serial I/O LOGIC CASCOUT Twos Complement Coding LOW PASS ANALOG A 2 IN DIGITAL Easy Interface to DSPs and Microcomputers MODULATOR FILTER RFS Software Control of Filter Cutoff OUTPUT SHIFT SDATA
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5 V Supply REGISTER LOW PASS SCLK Low Power Operation: 50 mW A 3 ANALOG IN MODULATOR DIGITAL FILTER DRDY APPLICATIONS Biomedical Data Acquisition LOW PASS ANALOG CONTROL A 4 ECG Machines IN DIGITAL MODULATOR REGISTER FILTER TFS EEG Machines Process Control High Accuracy Instrumentation VREF AGND DGND D 1 D 1 D 2 IN OUT OUT Seismic Systems GENERAL DESCRIPTION
There are 22 bits of data corresponding to the analog input. The AD7716 is a signal processing block for data acquisition Two bits contain the channel address and 3 bits are the device systems. It is capable of processing four channels with band- address. Thus, each channel in a 32-channel system would have widths of up to 584 Hz. Resolution is 22 bits and the usable a discrete 5-bit address. The device also has a CASCOUT pin dynamic range varies from 111 dB with an input bandwidth of and a CASCIN pin that allow simple networking of multiple 36.5 Hz to 99 dB with an input bandwidth of 584 Hz. devices. The device consists of four separate A/D converter channels that The on-chip control register is programmed using the SCLK, are implemented using sigma-delta technology. Sigma-delta SDATA and TFS pins. Three bits of the Control Register set ADCs include on-chip digital filtering and, thus, the system the digital filter cutoff frequency for the device. Selectable fre- filtering requirements are eased. quencies are 584 Hz, 292 Hz, 146 Hz, 73 Hz and 36.5 Hz. A further 2 bits appear as outputs DOUT1 and DOUT2 and can be Three address pins program the device address. This allows a used for controlling calibration at the front end. The device is data acquisition system with up to 32 channels to be set up in a available in a 44-pin PQFP (Plastic Quad Flatpack) and 44-pin simple fashion. The output word from the device contains 32 PLCC. bits of data. One bit is determined by the state of the DIN1 in- put and may be used, for example, in an ECG system with an external pacemaker detect circuit to indicate that the output word is invalid because of the presence of a pacemaker pulse. REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
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