Datasheet AD7714 (Analog Devices) - 8

AD7714 (AVDD = DVDD = +2.7 V to +5.25 V; AGND = DGND = 0 V; fCLKIN = 2.5␣ MHz; Input Logic 0 = 0 V, TIMING CHARACTERISTICS1, 2 Logic 1 = DVDD unless otherwise noted.) Limit at TMIN, TMAX Parameter (A, Y Versions) Units Conditions/Comments
f 3, 4 CLKIN 400 kHz min Master Clock Frequency: Crystal/Resonator or Externally Supplied 2.5 MHz max For Specified Performance
2
tCLK IN LO 0.4 × tCLK IN ns min Master Clock Input Low Time. tCLK IN = 1/fCLK IN tCLK IN HI 0.4 × tCLK IN ns min Master Clock Input High Time tDRDY 500 × tCLK IN ns nom DRDY High Time t1 100 ns min SYNC Pulsewidth t2 100 ns min RESET Pulsewidth Read Operation t3 0 ns min DRDY to CS Setup Time t4 0 ns min CS Falling Edge to SCLK Active Edge Setup Time5 t 6 5 0 ns min SCLK Active Edge to Data Valid Delay5 80 ns max DVDD = +5␣ V 100 ns max DVDD = +3␣ V t6 100 ns min SCLK High Pulsewidth t7 100 ns min SCLK Low Pulsewidth t8 0 ns min CS Rising Edge to SCLK Active Edge Hold Time5 t 7 9 10 ns min Bus Relinquish Time after SCLK Active Edge5 60 ns max DVDD = +5␣ V 100 ns max DVDD = +3␣ V t10 100 ns max SCLK Active Edge to DRDY High5, 8 Write Operation t11 0 ns min CS Falling Edge to SCLK Active Edge Setup Time5 t12 30 ns min Data Valid to SCLK Edge Setup Time t13 20 ns min Data Valid to SCLK Edge Hold Time t14 100 ns min SCLK High Pulsewidth t15 100 ns min SCLK Low Pulsewidth t16 0 ns min CS Rising Edge to SCLK Edge Hold Time NOTES 1Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of DV DD) and timed from a voltage level of 1.6 V. 2See Figures 6 and 7. Timing applies for all grades. 3CLKIN Duty Cycle range is 45% to 55%. CLKIN must be supplied whenever the AD7714 is not in standby mode. If no clock is present in this case, the device can draw higher current than specified and possibly become uncalibrated. 4The AD7714 is production tested with fCLKIN at 2.4576␣ MHz (1␣ MHz for some IDD tests). It is guaranteed by characterization to operate at 400␣ kHz. 5SCLK active edge is falling edge of SCLK with POL = 1; SCLK active edge is rising edge of SCLK with POL = 0. 6These numbers are measured with the load circuit of Figure 1 and defined as the time required for the output to cross the V OL or VOH limits. 7These numbers are derived from the measured time taken by the data output to change 0.5␣ V when loaded with the circuit of Figure 1. The measured number is then extrapolated back to remove effects of charging or discharging the 100 pF capacitor. This means that the times quoted in the timing characteristics are the true bus relinquish times of the part and as such are independent of external bus loading capacitances. 8DRDY returns high after the first read from the device after an output update. The same data can be read again, if required, while DRDY is high although care should be taken that subsequent reads do not occur close to the next output update. Specifications subject to change without notice.
ORDERING GUIDE AVDD Temperature Package Model Supply Range Option*
AD7714AN-5 5 V –40°C to +85°C N-24
ISINK (800
m
A AT DVDD = +5V
AD7714AR-5 5 V –40°C to +85°C R-24
100
m
A AT DVDD = +3.3V)
AD7714ARS-5 5 V –40°C to +85°C RS-28 AD7714AN-3 3 V –40°C to +85°C N-24
TO OUTPUT +1.6V
AD7714AR-3 3 V –40°C to +85°C R-24
PIN
AD7714ARS-3 3 V –40°C to +85°C RS-28
50pF
AD7714YN 3 V/5 V –40°C to +105°C N-24 AD7714YR 3 V/5 V –40°C to +105°C R-24
ISOURCE (200
m
A AT DVDD = +5V
AD7714YRU 3 V/5 V –40
100
m
A AT DV
°C to +105°C RU-24
DD = +3.3V)
AD7714AChips-5 5 V –40°C to +85°C Die AD7714AChips-3 3 V –40°C to +85°C Die Figure 1. Load Circuit for Access Time and Bus EVAL-AD7714-5EB 5 V Evaluation Board Relinquish Time EVAL-AD7714-3EB 3 V Evaluation Board *N = Plastic DIP; R = SOIC; RS = SSOP; RU = Thin Shrink Small Outline. REV. C –7–