Datasheet AD7896 (Analog Devices) - 8

AD7896 CONVERTER DETAILS
track-and-hold is greater than the Nyquist rate of the ADC even The AD7896 is a fast, 12-bit ADC that operates from a single when the ADC is operated at its maximum throughput rate of 2.7 V to 5.5 V supply. It provides the user with a track-and- 100 kHz (i.e., the track-and-hold can handle input frequencies hold, ADC, and serial interface logic functions on a single in excess of 50 kHz). chip. The ADC section of the AD7896 consists of a conven- The track-and-hold amplifier acquires an input signal to 12-bit tional successive approximation converter based on an R-2R accuracy in less than 1.5 µs. The operation of the track-and- ladder structure. The internal reference for the AD7896 is hold is essentially transparent to the user. With the high sampling derived from VDD, which allows the part to accept an analog operating mode, the track-and-hold amplifier goes from its input range of 0 V to VDD. The AD7896 has two operating tracking mode to its hold mode at the start of conversion (i.e., modes: the high sampling mode and the auto sleep mode the rising edge of CONVST). The aperture time for the track- where the part automatically goes into sleep after the end of and-hold (i.e., the delay time between the external CONVST conversion. These modes are discussed in more detail in the signal and the track-and-hold actually going into hold) is typi- Timing and Control section. cally 15 ns. At the end of conversion (on the falling edge of A major advantage of the AD7896 is that it provides all of the BUSY), the part returns to its tracking mode. The acquisition preceding functions in an 8-lead package, PDIP or SOIC. This time of the track-and-hold amplifier begins at this point. For the offers the user considerable space saving advantages over alterna- auto shutdown mode, the rising edge of CONVST wakes up the tive solutions. The AD7896 consumes only 9 mW typical, making part and the track-and-hold amplifier goes from its tracking it ideal for battery-powered applications. mode to its hold mode 6 µs after the rising edge of CONVST Conversion is initiated on the AD7896 by pulsing the CONVST (provided that the CONVST high time is less than 6 µs). Once input. On the falling edge of CONVST, the on-chip track-and- again the part returns to its tracking mode at the end of conver- hold goes from track to hold mode and the conversion sequence sion when the BUSY signal goes low. is started. The conversion clock for the part is generated inter-
Timing and Control
nally using a laser-trimmed clock oscillator circuit. Conversion Figure 2 shows the timing and control sequence required to time for the AD7896 is 8 µs in the high sampling mode (14 µs obtain optimum performance from the AD7896. In the for the auto sleep mode), and the track-and-hold acquisition sequence shown, conversion is initiated on the falling edge of time is 1.5 µs. To obtain optimum performance from the part, CONVST and new data from this conversion is available in the the read operation should not occur during the conversion or output register of the AD7896 8 µs later. Once the read opera- during 400 ns prior to the next conversion. This allows the part tion has taken place, another 400 ns should be allowed before to operate at throughput rates up to 100 kHz and achieves data the next falling edge of CONVST to optimize the settling of the sheet specifications (see the Timing and Control section). track-and-hold amplifier before the next conversion is initiated. With the serial clock frequency at its maximum of 10 MHz (5 V
CIRCUIT DESCRIPTION
operation), the achievable throughput time for the part is 8 µs
Analog Input Section
(conversion time) plus 1.6 µs (read time) plus 0.4 µs (acquisi- The analog input range for the AD7896 is 0 V to VDD. The tion time). This results in a minimum throughput time of 10 µs VIN pin drives the input to the track-and-hold amplifier directly. (equivalent to a throughput rate of 100 kHz). A serial clock of This allows for a maximum output impedance of the circuit less than 10 MHz can be used, but this will in turn mean that driving the analog input of 1 kΩ. This ensures that the part will the throughput time will increase. be settled to 12-bit accuracy in the 1.5 µs acquisition time. This The read operation consists of 16 serial clock pulses to the output input is benign with dynamic charging currents. The designed shift register of the AD7896. After 16 serial clock pulses, the shift code transitions occur on successive integer LSB values (i.e., register is reset and the SDATA line is three-stated. If there are 1 LSB, 2 LSB, 3 LSB, . , FS – 1 LSB). Output coding is straight more serial clock pulses after the 16th clock, the shift register will (natural) binary with 1 LSB = FS/4096 = 3.3 V/4096 = 0.81 mV. be moved on past its reset state. However, the shift register will be The ideal input/output transfer function is shown in Table I. reset again on the falling edge of the CONVST signal to ensure that the part returns to a known state every conversion cycle. As a
Table I. Ideal Input/Output Code Table for the AD7896
result, a read operation from the output register should not
Analog Input1 Code Transition
straddle across the falling edge of CONVST as the output shift register will be reset in the middle of the read operation and the +FSR – 1 LSB2 (3.299194) 111 . 110 to 111 . 111 data read back into the microprocessor will appear invalid. +FSR – 2 LSB (3.298389) 111 . 101 to 111 . 110 The throughput rate of the part can be increased by reading +FSR/2 – 3 LSB (3.297583) 111 . 100 to 111 . 101 data during conversion. If the data is read during conversion, a AGND + 3 LSB (0.002417) 000 . 010 to 000 . 011 throughput time of 8 µs (conversion time) plus 1.5 µs (acquisi- AGND + 2 LSB (0.001611) 000 . 001 to 000 . 010 tion time) is achieved when a 10 MHz, (5 V operation) serial AGND + 1 LSB (0.000806) 000 . 000 to 000 . 001 clock is being used. This minimum throughput time of 9.5 µs is NOTES achieved with a slight reduction in performance from the AD7896. 1FSR is full-scale range and is 3.3 V with VDD = +3.3 V. The advantage of this arrangement is that when the serial clock 21 LSB = FSR/4096 = 0.81 mV with VDD = +3.3 V. is significantly lower than 10 MHz, the throughput time for this
Track-and-Hold Section
arrangement will be significantly less than the throughput time The track-and-hold amplifier on the analog input of the AD7896 where the data is read after conversion. The signal-to-(noise + allows the ADC to accurately convert an input sine wave of full- distortion) number is likely to degrade by less than 1 dB while scale amplitude to 12-bit accuracy. The input bandwidth of the the code flicker from the part will also increase (see the AD7896 Performance section). Rev. D –7– Document Outline FEATURES GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS SPECIFICATIONS TIMING CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION PIN FUNCTION DESCRIPTIONS TERMINOLOGY Relative Accuracy Differential Nonlinearity Unipolar Offset Error Positive Full-Scale Error Track-and-Hold Acquisition Time Signal-to-(Noise + Distortion) Ratio Total Harmonic Distortion Peak Harmonic or Spurious Noise Intermodulation Distortion CONVERTER DETAILS CIRCUIT DESCRIPTION Analog Input Section Track-and-Hold Section Timing and Control OPERATING MODES Mode 1 Operation (High Sampling Performance) Mode 2 Operation (Auto Sleep after Conversion) Serial Interface MICROPROCESSOR/MICROCONTROLLER INTERFACE AD7896–8051 Interface AD7896–68HC11/L11 Interface AD7896–ADSP-2103/ADSP-2105 Interface AD7896–DSP56002/L002 Interface AD7896 PERFORMANCE Linearity Noise Dynamic Performance (Mode 1 Only) Effective Number of Bits Power Considerations OUTLINE DIMENSIONS ORDERING GUIDE Revision History