Datasheet AD7715 (Analog Devices) - 9

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AD7715 Data Sheet TIMING CHARACTERISTICS
DVDD = 3 V to 5.25 V; AVDD = 3 V to 5.25 V; AGND = DGND = 0 V; fCLKIN = 2.4576 MHz; Input Logic 0 = 0 V, Logic 1 = DVDD, unless otherwise noted.
Table 4. Limit at TMIN, TMAX Parameter1, 2 (A Version) Unit Conditions/Comments
f 3, 4 CLKIN 400 kHz min Master clock frequency: crystal oscillator or externally supplied for specified 2.5 MHz max performance tCLK IN LO 0.4 × tCLK IN ns min Master clock input low time; tCLK IN = 1/fCLK IN tCLK IN HI 0.4 × tCLK IN ns min Master clock input high time t1 500 × tCLK IN ns nom DRDY high time t2 100 ns min RESET pulsewidth Read Operation t3 0 ns min DRDY to CS setup time t4 120 ns min CS falling edge to SCLK rising edge setup time t 5 5 0 ns min SCLK falling edge to data valid delay 80 ns max DVDD = 5 V 100 ns max DVDD = 3.3 V t6 100 ns min SCLK high pulsewidth t7 100 ns min SCLK low pulsewidth t8 0 ns min CS rising edge to SCLK rising edge hold time t 6 9 10 ns min Bus relinquish time after SCLK rising edge 60 ns max DVDD = +5 V 100 ns max DVDD = +3.3 V t10 100 ns max SCLK falling edge to DRDY high7 Write Operation t11 120 ns min CS falling edge to SCLK rising edge setup time t12 30 ns min Data valid to SCLK rising edge setup time t13 20 ns min Data valid to SCLK rising edge hold time t14 100 ns min SCLK high pulsewidth t15 100 ns min SCLK low pulsewidth t16 0 ns min CS rising edge to SCLK rising edge hold time 1 Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.6 V. 2 See Figure 8 and Figure 9. 3 CLKIN Duty Cycle range is 45% to 55%. CLKIN must be supplied whenever the AD7715 is not in standby mode. If no clock is present in this case, the device can draw higher current than specified and possibly become uncalibrated. 4 The AD7715 is production tested with fCLKIN at 2.4576 MHz (1 MHz for some IDD tests). It is guaranteed by characterization to operate at 400 kHz. 5 These numbers are measured with the load circuit of Figure 2 and defined as the time required for the output to cross the VOL or VOH limits. 6 These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated back to remove effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus relinquish times of the part and as such are independent of external bus loading capacitances. 7 DRDY returns high after the first read from the device after an output update. The same data can be read again, if required, while DRDY is high although take care that subsequent reads do not occur close to the next output update.
ISINK (800µA AT DVDD = 5V 100µA AT DVDD = 3.3V) TO OUTPUT +1.6V PIN 50pF ISOURCE (200µA AT DVDD = 5V
002
100µA AT DVDD = 3.3V)
08519- Figure 2. Load Circuit for Access Time and Bus Relinquish Time Rev. E | Page 8 of 40 Document Outline FEATURES FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS AD7715-5 AD7715-3 TIMING CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TERMINOLOGY ON-CHIP REGISTERS COMMUNICATIONS REGISTER (RS1, RS0 = 0, 0) SETUP REGISTER (RS1, RS0 = 0, 1); POWER ON/RESET STATUS: 28 HEX TEST REGISTER (RS1, RS0 = 1, 0) DATA REGISTER (RS1, RS0 = 1, 1) OUTPUT NOISE AD7715-5 AD7715-3 CALIBRATION SEQUENCES CIRCUIT DESCRIPTION ANALOG INPUT Analog Input Ranges Input Sample Rate Bipolar/Unipolar Inputs REFERENCE INPUT DIGITAL FILTERING Filter Characteristics Post-Filtering ANALOG FILTERING CALIBRATION Self-Calibration System Calibration Span and Offset Limits Power-Up and Calibration USING THE AD7715 CLOCKING AND OSCILLATOR CIRCUIT SYSTEM SYNCHRONIZATION RESET INPUT STANDBY MODE ACCURACY DRIFT CONSIDERATIONS POWER SUPPLIES Supply Current Grounding and Layout Evaluating the AD7715 Performance DIGITAL INTERFACE CONFIGURING THE AD7715 MICROCONTROLLER/MICROPROCESSOR INTERFACING AD7715 TO 68HC11 INTERFACE AD7715 TO 8XC51 INTERFACE AD7715 TO ADSP-2184N/ADSP-2185N/ ADSP-2186N/ADSP-2187N/ADSP-2188N/ ADSP-2189N INTERFACE CODE FOR SETTING UP THE AD7715 C CODE FOR INTERFACING AD7715 TO 68HC11 APPLICATIONS INFORMATION PRESSURE MEASUREMENT TEMPERATURE MEASUREMENT SMART TRANSMITTERS OUTLINE DIMENSIONS ORDERING GUIDE