Datasheet AD7715 (Analog Devices) - 5

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AD7715 Data Sheet Parameter1 Min Typ Max Unit Conditions/Comments
LOGIC OUTPUTS (Including MCLK OUT) VOL, Output Low Voltage 0.4 V ISINK = 800 µA except for MCLK OUT12; DVDD = 5 V VOL, Output Low Voltage 0.4 V ISINK = 100 µA except for MCLK OUT12; DVDD = 3.3 V VOH, Output High Voltage 4.0 V ISOURCE = 200 µA except for MCLK OUT12; DVDD = 5 V VOH, Output High Voltage DVDD − 0.6 V ISOURCE = 100 µA except for MCLK OUT12; DVDD = 3.3 V Floating State Leakage Current ±10 µA Floating State Output Capacitance13 9 pF Data Output Coding Binary Unipolar mode Offset binary Bipolar mode 1 Temperature range as follows: A version, −40°C to +85°C. 2 A calibration is effectively a conversion, so these errors are of the order of the conversion noise shown in Table 15 to Table 22. This applies after calibration at the temperature of interest. 3 Recalibration at any temperature removes these drift errors. 4 Positive full-scale error includes zero-scale errors (unipolar offset error or bipolar zero error) and applies to both unipolar and bipolar input ranges. 5 Full-scale drift includes zero-scale drift (unipolar offset drift or bipolar zero drift) and applies to both unipolar and bipolar input ranges. 6 Gain error does not include zero-scale errors. It is calculated as ful -scale error–unipolar offset error for unipolar ranges and full-scale error–bipolar zero error for bipolar ranges. 7 Gain error drift does not include unipolar offset drift/bipolar zero drift. It is effectively the drift of the part if zero scale calibrations only were performed. 8 These numbers are guaranteed by design and/or characterization. 9 This common-mode voltage range is allowed provided that the input voltage on AIN(+) or AIN(−) does not go more positive than AVDD + 30 mV or go more negative than AGND − 30 mV. 10 The analog input voltage range on AIN(+) is given here with respect to the voltage on AIN(−). The absolute voltage on the analog inputs should not go more positive than AVDD + 30 mV or go more negative than AGND − 30 mV. 11 VREF = REF IN(+) − REF IN(−). 12 These logic output levels apply to the MCLK OUT only when it is loaded with one CMOS load. 13 Sample tested at 25°C to ensure compliance. Rev. E | Page 4 of 40 Document Outline FEATURES FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS AD7715-5 AD7715-3 TIMING CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TERMINOLOGY ON-CHIP REGISTERS COMMUNICATIONS REGISTER (RS1, RS0 = 0, 0) SETUP REGISTER (RS1, RS0 = 0, 1); POWER ON/RESET STATUS: 28 HEX TEST REGISTER (RS1, RS0 = 1, 0) DATA REGISTER (RS1, RS0 = 1, 1) OUTPUT NOISE AD7715-5 AD7715-3 CALIBRATION SEQUENCES CIRCUIT DESCRIPTION ANALOG INPUT Analog Input Ranges Input Sample Rate Bipolar/Unipolar Inputs REFERENCE INPUT DIGITAL FILTERING Filter Characteristics Post-Filtering ANALOG FILTERING CALIBRATION Self-Calibration System Calibration Span and Offset Limits Power-Up and Calibration USING THE AD7715 CLOCKING AND OSCILLATOR CIRCUIT SYSTEM SYNCHRONIZATION RESET INPUT STANDBY MODE ACCURACY DRIFT CONSIDERATIONS POWER SUPPLIES Supply Current Grounding and Layout Evaluating the AD7715 Performance DIGITAL INTERFACE CONFIGURING THE AD7715 MICROCONTROLLER/MICROPROCESSOR INTERFACING AD7715 TO 68HC11 INTERFACE AD7715 TO 8XC51 INTERFACE AD7715 TO ADSP-2184N/ADSP-2185N/ ADSP-2186N/ADSP-2187N/ADSP-2188N/ ADSP-2189N INTERFACE CODE FOR SETTING UP THE AD7715 C CODE FOR INTERFACING AD7715 TO 68HC11 APPLICATIONS INFORMATION PRESSURE MEASUREMENT TEMPERATURE MEASUREMENT SMART TRANSMITTERS OUTLINE DIMENSIONS ORDERING GUIDE