Datasheet AD7891 (Analog Devices) - 5

AD7891 TIMING CHARACTERISTICS1, 2 Parameter A, B, Y Versions Unit Test Conditions/Comments
tCONV 1.6 ms max Conversion Time Parallel Interface t1 0 ns min CS to RD/WR Setup Time t2 35 ns min Write Pulse Width t3 25 ns min Data Valid to Write Setup Time t4 5 ns min Data Valid to Write Hold Time t5 0 ns min CS to RD/WR Hold Time t6 35 ns min CONVST Pulse Width t7 55 ns min EOC Pulse Width t8 35 ns min Read Pulse Width t 3 9 25 ns min Data Access Time after Falling Edge of RD t 4 10 5 ns min Bus Relinquish Time after Rising Edge of RD 30 ns max Serial Interface t11 30 ns min RFS Low to SCLK Falling Edge Setup Time t 3 12 20 ns max RFS Low to Data Valid Delay t13 25 ns min SCLK High Pulse Width t14 25 ns min SCLK Low Pulse Width t 3 15 5 ns min SCLK Rising Edge to Data Valid Hold Time t 3 16 15 ns max SCLK Rising Edge to Data Valid Delay t17 20 ns min RFS to SCLK Falling Edge Hold Time t 4 18 0 ns min Bus Relinquish Time after Rising Edge of RFS 30 ns max t 4 18A 0 ns min Bus Relinquish Time after Rising Edge of SCLK 30 ns max t19 20 ns min TFS Low to SCLK Falling Edge Setup Time t20 15 ns min Data Valid to SCLK Falling Edge Setup Time t21 10 ns min Data Valid to SCLK Falling Edge Hold Time t22 30 ns min TFS Low to SCLK Falling Edge Hold Time NOTES 1Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are measured with tr = tf = 1 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V. 2See Figures 2, 3, and 4. 3Measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V. 4These times are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus relinquish times of the part and as such are independent of external bus loading capacitances. Specifications subject to change without notice.
1.6mA TO OUTPUT 1.6V PIN 50pF 200
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A
Figure 1. Load Circuit for Access Time and Bus Relinquish Time –4– REV. D Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS TIMING CHARACTERISTICS ORDERING GUIDE PIN CONFIGURATIONS PIN FUNCTION DESCRIPTIONS PARALLEL INTERFACE MODE FUNCTIONS Data I/O Lines Parallel Read Operation SERIAL INTERFACE MODE FUNCTIONS CONTROL REGISTER TERMINOLOGY Signal-to-(Noise + Distortion) Ratio Total Harmonic Distortion (THD) Peak Harmonic or Spurious Noise Intermodulation Distortion Channel-to-Channel Isolation Relative Accuracy Differential Nonlinearity Positive Full-Scale Error (AD7891-1, ±10 V and ±5 V; AD7891-2, ±2.5 V) Positive Full-Scale Error (AD7891-2, 0 V to 5 V and 0 V to 2.5 V) Bipolar Zero Error (AD7891-1, ±10 V and ±5 V; AD7891-2, ±2.5 V) Unipolar Offset Error (AD7891-2, 0 V to 5 V and 0 V to 2.5 V) Negative Full-Scale Error (AD7891-1, ±10 V and ±5V; AD7891-2, ±2.5 V) Track/Hold Acquisition Time CONVERTER DETAILS INTERFACE INFORMATION Parallel Interface Mode Serial Interface Mode Simplifying the Serial Interface CIRCUIT DESCRIPTION Reference Analog Input Section Track/Hold Amplifier STANDBY Operation MICROPROCESSOR INTERFACING AD7891 to 8X51 Serial Interface AD7891 to 68HC11 Serial Interface AD7891 to ADSP-21xx Serial Interface AD7891 to DSP5600x Serial Interface AD7891 to TMS320xxx Serial Interface PARALLEL INTERFACING AD7891 to ADSP-21xx AD7891 to TMS32020, TMS320C25, and TMS320C5x AD7891 to TMS320C3x AD7891 to DSP5600x Power Supply Bypassing and Grounding AD7891 PERFORMANCE Linearity Noise Dynamic Performance Effective Number of Bits OUTLINE DIMENSIONS Revision History