Datasheet AD7721 (Analog Devices) - 7

AD7721 PIN FUNCTION DESCRIPTIONS Mnemonic Function
AVDD Analog Positive Supply Voltage, +5 V ± 5%. AGND Ground reference point for analog circuitry. DVDD Digital Supply Voltage, +5 V ± 5%. DGND Ground reference point for digital circuitry. DGND must be connected via its own short path to AGND (Pin 24). DSUBST This is the substrate connection for digital circuits. It must be connected via its own short path to AGND (Pin 24). VIN1 Analog Input. In unipolar operation, the analog input range on VIN1 is VIN2 to (VIN2 + VREFIN); for bipolar VIN2 operation, the analog input range on VIN1 is (VIN2 ± VREFIN/2). The absolute analog input range must lie between 0 and AVDD. The analog input is continuously sampled and processed by the analog modulator. REFIN Reference Input. The AD7721 operates with an external reference, of value 2.5 V nominal. A suitable refer- ence for operation with the AD7721 is the AD780. A 100 nF decoupling capacitor is required between REFIN and AGND. CLK CMOS Logic Clock Input. The AD7721 operates with an external clock which is connected to the CLK pin. The modulator samples the analog input on both phases of the clock, increasing the sampling rate to 20 MHz (CLK = 10 MHz) or 30 MHz (CLK = 15 MHz).
Serial Mode Only
CS, RD, WR To select the serial interface mode of operation, the AD7721 must be powered up with CS, RD and WR all tied to DGND. After two clock cycles, the AD7721 switches into serial mode. These pins must remain low during serial operation. DRDY In the serial interface mode, a rising edge on DRDY indicates that new data is available to be read from the interface. During a synchronization or calibration cycle, DRDY remains low until valid data is available. SDATA/DB11 Serial Data Output. Output serial data becomes active after RFS goes low. Sixteen bits of data are clocked out starting with the MSB. Serial data is clocked out on the rising edge of SCLK and is valid on the subse- quent falling edge of SCLK. RFS/DB10 Receive Frame Synchronization. Active low logic input. This is a logic input with RFS provided by connect- ing this input to DRDY. When RFS is high, SDATA is high impedance. DB9 This is a test mode pin. This pin must be tied to DGND. DB8 This is a test mode pin. This pin must be tied to DGND. SCLK/DB7 Serial Clock. Logic Output. The internal digital clock is provided as an output on this pin. Data is output from the AD7721 on the rising edge of SCLK and is valid on the falling edge of SCLK. DB6 This is a test mode pin. This pin must be tied to DGND. SYNC/DB5 Synchronization Logic Input. A rising edge on SYNC starts the synchronization cycle. SYNC must be pulsed low for at least one clock cycle to initiate a synchronization cycle. DB4 This is a test mode pin. This pin must be tied to DGND. DB3 This is a test mode pin. This pin must be tied to DGND. UNI/DB2 Analog Input Range Select, Logic Input. A logic low on this input selects unipolar mode. A logic high selects bipolar mode. CAL/DB1 Calibration Mode Logic Input. CAL must go high for at least one clock cycle to initiate a calibration cycle. STBY/DB0 Standby Mode Logic Input. A logic high on this pin selects standby mode. DVAL/SYNC Data Valid Digital Output. In serial mode, this pin is a dedicated data valid pin. –6– REV. A