Datasheet AD9221, AD9223, AD9220 (Analog Devices) - 9

AD9221/AD9223/AD9220 INTRODUCTION
also similar. The data sheet is structured such that the designer The AD9221/AD9223/AD9220 are members of a high perfor- can make an informed decision in selecting the proper A/D and mance, complete single-supply 12-bit ADC product family based optimizing its performance to fit the specific application. on the same CMOS pipelined architecture. The product family allows the system designer an upward or downward component
0
selection path based on dynamic performance, sample rate, and
AD9220
power. The analog input range of the AD9221/AD9223/AD9220 is highly flexible, allowing for both single-ended or differen-
–3 AD9223
tial inputs of varying amplitudes that can be ac or dc coupled. Each device shares the same interface options, pinout, and package offering.
–6
The AD9221/AD9223/AD9220 utilize a four-stage pipeline
AD9221 AMPLITUDE – dB
architecture with a wideband input sample-and-hold amplifier (SHA) implemented on a cost-effective CMOS process. Each
–9
stage of the pipeline, excluding the last stage, consists of a low resolution flash A/D connected to a switched capacitor DAC and interstage residue amplifier (MDAC). The residue amplifier
–12 1 10 100
amplifies the difference between the reconstructed DAC output
FREQUENCY – MHz
and the flash input for the next stage in the pipeline. One bit of redundancy is used in each of the stages to facilitate digital Figure 2. Full-Power Bandwidth correction of flash errors. The last stage simply consists of a flash A/D.
4000
The pipeline architecture allows a greater throughput rate at the
AD9220
expense of pipeline delay or latency. This means that while the
AD9223 AD9221
converter is capable of capturing a new input sample every clock
3000
cycle, it actually takes three clock cycles for the conversion to be fully processed and appear at the output. This latency is not a concern in most applications. The digital output, together with
2000 CODE
the out-of-range indicator (OTR), is latched into an output buffer to drive the output pins. The output drivers can be configured to interface with 5 V or 3.3 V logic families.
1000
The AD9221/AD9223/AD9220 use both edges of the clock in their internal timing circuitry (see Figure 1 and Specifications
0
for exact timing requirements). The A/D samples the analog
0 10 20 30 40 50 60
input on the rising edge of the clock input. During the clock low
SETTLING TIME – ns
time (between the falling edge and rising edge of the clock), the input SHA is in the sample mode; during the clock high time, it Figure 3. Settling Time is in hold. System disturbances just prior to the rising edge of the clock and/or excessive clock jitter may cause the input SHA
ANALOG INPUT AND REFERENCE OVERVIEW
to acquire the wrong value, and should be minimized. Figure 4, a simplified model of the AD9221/AD9223/AD9220, highlights the relationship between the analog inputs, VINA, The internal circuitry of both the input SHA and individual VINB, and the reference voltage, VREF. Like the voltage pipeline stages of each member of the product family are opti- applied to the top of the resistor ladder in a flash A/D converter, mized for both power dissipation and performance. An inherent the value VREF defines the maximum input voltage to the A/D trade-off exists between the input SHA’s dynamic performance core. The minimum input voltage to the A/D core is automati- and its power dissipation. Figures 2 and 3 show this trade-off by cally defined to be –VREF. comparing the full-power bandwidth and settling time of the AD9221/AD9223/AD9220. Both figures reveal that higher full- power bandwidths and faster settling times are achieved at the
AD9221/AD9223/AD9220
expense of an increase in power dissipation. Similarly, a trade-
VINA +VREF
off exists between the sampling rate and the power dissipated
VCORE 12 A/D
in each stage.
CORE
As previously stated, the AD9221, AD9223, and AD9220 are
VINB –V
similar in most aspects except for the specified sampling rate,
REF
power consumption, and dynamic performance. The product Figure 4. AD9221/AD9223/AD9220 Equivalent family is highly flexible, providing several different input ranges Functional Input Circuit and interface options. As a result, many of the application issues and trade-offs associated with these resulting configurations are REV. E –9– Document Outline FEATURES GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ORDERING GUIDE PIN CONFIGURATION PIN FUNCTION DESCRIPTIONS DEFINITIONS OF SPECIFICATIONS Integral Nonlinearity (INL) Differential Nonlinearity (DNL, No Missing Codes) Zero Error Gain Error Temperature Drift Power Supply Rejection Aperture Jitter Aperture Delay Signal-to-Noise and Distortion (S/N+D, SINAD) Ratio Effective Number of Bits (ENOB) Total Harmonic Distortion (THD) Signal-to-Noise Ratio (SNR) Spurious Free Dynamic Range (SFDR) Typical Performance Characteristics INTRODUCTION ANALOG INPUT AND REFERENCE OVERVIEW ANALOG INPUT OPERATION REFERENCE OPERATION DRIVING THE ANALOG INPUTS Introduction SINGLE-ENDED MODE OF OPERATION DC COUPLING AND INTERFACE ISSUES Simple Op Amp Buffer Op Amp with DC Level Shifting AC COUPLING AND INTERFACE ISSUES Simple AC Interface Alternative AC Interface Op Amp Selection Guide DIFFERENTIAL MODE OF OPERATION REFERENCE CONFIGURATIONS USING THE INTERNAL REFERENCE Single-Ended Input with 0 to 2 VREF Range Single-Ended or Differential Input, VCM = 2.5 V VINA Resistor Programmable Reference USING AN EXTERNAL REFERENCE Variable Input Span with VCM = 2.5 V Single-Ended Input with 0 to 2 VREF Range Low Cost/Power Reference DIGITAL INPUTS AND OUTPUTS Digital Outputs Out Of Range (OTR) Digital Output Driver Considerations (DVDD) Clock Input and Considerations GROUNDING AND DECOUPLING Analog and Digital Grounding Analog and Digital Supply Decoupling APPLICATIONS Direct IF Down Conversion Using the AD9220 Multichannel Data Acquisition with Autocalibration OUTLINE DIMENSIONS Revision History