Datasheet AD10242 (Analog Devices) - 6

AD10242 PIN CONFIGURATION 68-Lead Ceramic Leaded Chip Carrier A3 A2 A1 EE CC B3 B2 B1 IN IN IN IN IN IN GNDA A A A GNDA UCOMA UNEGA GNDA SHIELD GNDB AV AV GNDB A A A GNDB 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 GNDA 10 PIN 1 60 GNDB IDENTIFIER GNDA 11 59 GNDB UPOSA 12 58 GNDB AV 13 57 EE UPOSB AV 14 CC 56 UNEGB NC 15 55 UCOMB NC 16 54 GNDB (LSB) D0A 17 AD10242 53 GNDB D1A 18 TOP VIEW 52 ENCODEB (Not to Scale) D2A 19 51 ENCODEB 20 D3A 50 DVCC D4A 21 49 D11B (MSB) 22 D5A 48 D10B 23 D6A 47 D9B 24 D7A 46 D8B 25 D8A 45 D7B 26 GNDA 44 GNDB 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 CC NC NC D9A D1B D2B D3B D4B D5B D6B GNDA DV D10A GNDB NC = NO CONNECT ENCODEA ENCODEA (LSB) D0B (MSB) D11A PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Function
1 SHIELD Internal Ground Shield between Channels. 2, 5, 9–11, 26–27 GNDA A Channel Ground. A and B grounds should be connected as close to the device as possible. 3 UNEGA Unipolar Negative. 4 UCOMA Unipolar Common. 6 AINA1 Analog Input for A Side ADC (Nominally ± 0.5 V). 7 AINA2 Analog Input for A Side ADC (Nominally ± 1.0 V). 8 AINA3 Analog Input for A Side ADC (Nominally ± 2.0 V). 12 UPOSA Unipolar Positive. 13 AVEE Analog Negative Supply Voltage (Nominally –5.0 V or –5.2 V). 14 AVCC Analog Positive Supply Voltage (Nominally 5.0 V). 15, 16, 34, 35 NC No Connect. 17–25, 31–33 D0A–D11A Digital Outputs for ADC A. (D0 LSB.) 28 ENCODEA ENCODE is the complement of ENCODE. 29 ENCODEA Data conversion is initiated on the rising edge of the ENCODE input. 30, 50 DVCC Digital Positive Supply Voltage (Nominally 5.0 V). 36–42, 45–49 D0B–D11B Digital Outputs for ADC B. (D0 LSB.) 43–44, 53–54, GNDB B Channel Ground. A and B grounds should be connected as close to the device 58–61, 65, 68 as possible. 51 ENCODEB Data conversion is initiated on the rising edge of the ENCODE input. 52 ENCODEB ENCODE is the complement of ENCODE. 55 UCOMB Unipolar Common. 56 UNEGB Unipolar Negative. 57 UPOSB Unipolar Positive. 62 AINB1 Analog Input for B Side ADC (Nominally ± 0.5 V). 63 AINB2 Analog Input for B Side ADC (Nominally ± 1.0 V). 64 AINB3 Analog Input for B Side ADC (Nominally ± 2.0 V). 66 AVCC Analog Positive Supply Voltage (Nominally 5.0 V). 67 AVEE Analog Negative Supply Voltage (Nominally –5.0 V or –5.2 V). REV. D –5– Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION PRODUCT HIGHLIGHTS FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS1 EXPLANATION OF TEST LEVELS PIN CONFIGURATION PIN FUNCTION DESCRIPTIONS DEFINITION OF SPECIFICATIONS Analog Bandwidth Aperture Delay Aperture Uncertainty (Jitter) Differential Nonlinearity Encode Pulsewidth/Duty Cycle Harmonic Distortion Integral Nonlinearity Minimum Conversion Rate Maximum Conversion Rate Output Propagation Delay Overvoltage Recovery Time Power Supply Rejection Ratio Signal-to-Noise and Distortion (SINAD) Signal-to-Noise Ratio (SNR, without Harmonics) Spurious-Free Dynamic Range (SFDR) Transient Response Two-Tone Intermodulation Distortion Rejection Two-Tone SFDR EQUIVALENT CIRCUITS Typical Performance Characteristics THEORY OF OPERATION APPLYING THE AD10242 Encoding the AD10242 Performance Improvements USING THE FLEXIBLE INPUT GROUNDING AND DECOUPLING Analog and Digital Grounding LAYOUT INFORMATION EVALUATION BOARD OUTLINE DIMENSIONS Ordering Guide Revision History